PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 61

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

Access in multiplexed P-interface mode:
4.2.3
4.2.3.1 Memory Access Control Register (MACR)
Access in demultiplexed P-interface mode:
Reset value: xx
With the MACR the P selects the type of memory (CM or DM), the type of field (data or
code) and the access mode (read or write) of the register access. When writing to the
control memory code field, MACR also contains the 4 bit code (CMC3..0) defining the
function of the addressed CFI time slot.
RWS
MOC3..0 Memory Operation Code.
CMC3..0
Note: Prior to a new access to any memory location (i.e. writing to MACR) the
Semiconductor Group
bit 7
RWS
STAR:MAC bit must be polled for “0”.
Memory Access Registers
Read/Write Select.
0…write operation on control or data memories
1…read operation on control or data memories
Control Memory Code.
These bits determine the type and destination of the memory operation as
shown below.
MOC3
H
MOC2
MOC1
61
MOC0
CMC3
read/write
read/write
Detailed Register Description
CMC2
address: 0
OMDR:RBS = 0
address: 00
CMC1
PEB 2055
PEF 2055
H
bit 0
H
CMC0