PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 81

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

PTL
COS
MFPS
CSB
RBS
PSB
Semiconductor Group
PCM Standby.
0…the PCM interface output pins TxD0..3 are set to high impedance and
1…the PCM output pins transmit the contents of the upstream data memory
PCM Test Loop.
0…the PCM test loop is disabled.
1…the PCM test loop is enabled, i.e. the physical transmit pins TxD# are
CFI Output driver Selection.
0…the CFI output drivers are tristate drivers.
1…the CFI output drivers are open drain drivers.
Monitor/Feature control channel Protocol Selection.
0…handshake facility disabled (SLD and IOM-1 applications)
1…handshake facility enabled (IOM-2 applications)
CFI Standby.
0…the CFI interface output pins DD0..3, DU0..3, DCL and FSC are set to
1…the CFI output pins are active.
Register Bank Selection. Used in demultiplexed data/address modes only.
those TSC pins that are actually used as tristate control signals are set
to logical 1 (inactive).
or may be set to high impedance via the data memory tristate field.
internally connected to the corresponding physical receive pins RxD#,
such that data transmitted over TxD# are internally looped back to RxD#
and data externally received over RxD# are ignored. The TxD# pins still
output the contents of the upstream data memory according to the setting
of the tristate field (only modes 0 and 1; mode 1 with AIS bit set).
high impedance.
0…to access the registers used during device operation
1…to access the registers used during device initialization.
81
Detailed Register Description
PEB 2055
PEF 2055