PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 179

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

Table 29
Transferred Channel PCM
Bit Positions
Unassigned channel
16 kbit/s/ bits 7 … 6
16 kbit/s/ bits 5 … 4
16 kbit/s/ bits 3 … 2
16 kbit/s/ bits 1 … 0
logical 1; the MR and MX bit positions can then, if required, be accessed together with
the 4 bit C/I field via the even control memory address.
The D-Channel can be switched as a 16 kbit/s channel to and from the PCM interface in
order to be handled by a centralized D-Channel processing unit.
The 4 bit C/I channel can be accessed by the P for controlling layer-1 devices. In the
upstream direction each change in the C/I value is reported by interrupt to the P and
the CFI time slot address is stored in the CIFIFO (refer to chapter 5.5.2). A C/I change
is detected if the value of the current CFI frame is different from the value of the previous
frame i.e. after at most 125 s.
To initialize two consecutive CFI time slots for the decentral D-Channel handling
scheme, the CM codes as given in table 28 must be used.
Table 28
CM Address
Even time slot downstream
Odd time slot downstream
Even time slot upstream
Odd time slot upstream
The switching codes specify the PCM subtime slot positions of the 16 kbit/s transfer.
Note that the 2 D bits are always located on bits 7 … 6 of a CFI time slot, the
CSCR:SC#1, SC#0 bits must therefore be set to 00 (see chapter 5.4.2).
1)
Semiconductor Group
This code sets the D bits to high impedance
CM Code
1010
Switching code
1000
Switching code
Downstream CM Codes
1011
0111
0110
0101
0100
1)
179
CM Data
11 C/I 11
Pointer to PCM TS
XX C/I XX
Pointer to PCM TS
Upstream CM Codes
0000
0111
0110
0101
0100
B
Application Hints
B
PEB 2055
PEF 2055