PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 227

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

ISTA:
checked by the EPIC for spikes that may disturb the proper operation of the EPIC. If such
an inappropriate clocking or power failure occurs, data in the internal memories may be
lost, and a reinitialization of the EPIC is necessary. An Initialization Request status bit
(VNSR:IR) can be interrogated periodically by the P to determine the current status of
the device.
In normal chip operation, the IR bit should never be set, not even after power on or when
the clock signals are switched on and off. The IR bit will only be set if spikes ( 10 ns)
are detected on the clock and power lines which may affect the data transfer on the EPIC
internal buses.
The following register bits are used in conjunction with the PCM framing supervision:
Interrupt Status Register
The ISTA register should be read after an interrupt in order to determine the interrupt
source. In connection with the PCM framing control one maskable (MASK) interrupt bit
is provided by the EPIC:
PFI:
Status Register
STAR:
The STAR register bits do not generate interrupts and are not modified by reading
STAR. However, each change of the PSS bit (0
interrupt.
PSS:
5.8.4
Power and Clock Supply Supervision
The + 5 V power supply line (
Semiconductor Group
Power and Clock Supply Supervision/Chip Version
bit 7
bit 7
MAC
TIN
PCM Framing Interrupt; if this bit is set to logical 1, the STAR:PSS bit
has changed its polarity. To determine whether the PCM interface is
synchronized or not, STAR must be read. The PFI bit is reset by
reading ISTA.
PCM
synchronized, the PSS bit is set to logical 1. The PSS bit is reset to
logical 0 if there is a mismatch between the PBNR value and the
applied clock and framing signals (PDC/PFS) or if OMDR:OMS0 = 0.
SFI
TAC
Synchronization
MFFI
V
PSS
DD
) and the reference clock (RCL) are continuously
MFTO
MAC
227
read/write reset value:
read
Status;
MFAB
PFI
1 and 1
while
reset value:
MFAE
PIM
the PCM
0) causes an ISTA:PFI
Application Hints
MFRW
SIN
00
05
interface
PEB 2055
H
H
PEF 2055
bit 0
bit 0
MFFE
SOV
is