PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 217

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

SAXB:
Synchronous Transfer Control
Register STCR
STCR:
The STCR register bits are used to enable or disable the synchronous transfer utility and
to determine the subtime slot bandwidth and position if a PCM interface time slot is
involved.
TAE, TBE:
CTA2 … 0:
CTB2 … 0:
Synchronous Transfer Transmit
Address Register B
The SAXB register specifies for synchronous transfer channel B to which output
interface, port, and time slot the serial data contained in the STDB register is sent.
ISXB:
MTXB6 … 0:
Semiconductor Group
bit 7
bit 7
ISXB
TBE
Interface Select Transmit for channel B; selects the PCM interface
(ISXB = 0) or the CFI (ISXB = 1) as the output interface for
synchronous channel B.
slot number at the interface selected by ISXB according to figure 48:
MTXB6 … 0 = MA6 … 0.
Transfer Channel A (B) Enable; A logical 1 enables the P transfer, a
logical 0 disables the transfer of the corresponding channel.
Channel Type A (B); these bits determine the bandwidth of the
channel and the position of the relevant bits in the time slot according
to table 33. Note that if a CFI time slot is selected as receive or
transmit time slot of the synchronous transfer, the 64 kbit/s bandwidth
must be selected (CT#2 … CT#0 = 001).
P Transfer Transmit Address for channel B; selects the port and time
MTXB6 MTXB5 MTXB4 MTXB3 MTXB2 MTXB1 MTXB0
TAE
CTB2
CTB1
217
read/write reset value:
read/write reset value:
CTB0
CTA2
Application Hints
CTA1
undefined
undefined
PEB 2055
PEF 2055
bit 0
bit 0
CTA0