PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 75

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

Access in multiplexed P-interface mode:
The status register STAR displays the current state of certain events within the EPIC.
The STAR register bits do not generate interrupts and are not modified by reading
STAR.
MAC
4.2.6.3 Status Register (STAR)
Access in demultiplexed P-interface mode:
Reset value: 05
TAC
PSS
MFTO
MFAB
MFAE
MFRW
MFFE
Semiconductor Group
bit 7
MAC
Memory Access
0…no memory access is in operation.
1… a memory access is in operation. Hence, the memory access registers
may not be used.
Timer Active
0… the timer is stopped.
1… the timer is running.
PCM Synchronization Status.
1… the PCM interface is synchronized.
0… the PCM interface is not synchronized. There is a mismatch between the
PBNR value and the applied clock and framing signals (PDC/PFS) or
OMDR:OMS0 = 0.
MF Channel Transfer in Operation.
0… no MF channel transfer is in operation.
1… an MF channel transfer is in operation.
MF Channel Transfer Aborted.
0… the remote receiver did not abort a handshake message transfer.
1… the remote receiver aborted a handshake message transfer.
MFFIFO Access Enable.
0… the MFFIFO may not be accessed.
1… the MFFIFO may be either read or written to.
MFFIFO Read/Write.
0… the MFFIFO is ready to be written to.
1… the MFFIFO may be read.
MFFIFO Empty
0… the MFFIFO is not empty.
1… the MFFIFO is empty.
Note:MAC is also set and reset during synchronous transfers.
TAC
H
PSS
MFTO
75
MFAB
read
read
Detailed Register Description
MFAE
address: D
OMDR:RBS = 0
address: 1A
MFRW
PEB 2055
PEF 2055
H
bit 0
H
MFFE