GCIXP1200GC Intel, GCIXP1200GC Datasheet - Page 21

• Manufacturer Part Number: GCIXP1200GC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839429

5.5
Datasheet
PCI Unit
The PCI Unit provides an industry standard 32-bit PCI Bus to interface to PCI peripheral devices
such as host processors and MAC devices. The PCI Unit supports operating speeds from DC up to
66 MHz, and supports PCI Local Bus Specification, Revision 2.2. This unit contains:
Refer to the Intel
PCI Bus behavior for Target (Slave) and Initiator (Master) modes, configuration and register
definitions.
The PCI interface is specified to operate from DC up to 66 MHz. Above 33 MHz operation, two
PCI devices are supported only, the IXP1200 and a second PCI device. To increase the number of
PCI devices supported or to add connectors to the bus at the higher PCI Bus speeds, a PCI-to-PCI
bridge device, such the Intel 21150, 21152, or 21153 is required.
Both PCI Initiator and Target cycles are supported. As a target device, the IXP1200 responds as a
Medium Speed device asserting DEVSEL# two PCI_CLK cycles after FRAME# is asserted.
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Accesses from the StrongARM* core:
Accesses from the Microengines:
Arbitration logic to support up to three PCI Bus masters,
PCI Intelligent I/O (I
Two DMA channels, and
Four 24-bit timers.
— Byte, word, and longword accesses generated from the StrongARM* core are supported.
— Bit operations are supported via StrongARM* core accesses to the SRAM Alias Address
— Bit, byte, and word writes result in Read-Modify-Write cycles.
— Declare memory-mapped I/O as non-cachable to prevent line fill burst cycles, and disable
— For best performance, use longword accesses to avoid Read-Modify-Write cycles on the
— The sram microinstruction defines the number of 32-bit accesses to make, up to 8
— Only bit and longword accesses are supported.
— Bit write accesses result in Read-Modify-Write cycles.
— Unlike the StrongARM* core, the Microengine microinstruction allows you to perform
Space to perform the same operations as a Microengine can accomplish implicitly in a
microinstruction (Push, Pop, Bit Test and Set, CAM operations, Lock/Unlock, etc.).
caching and write buffering to ensure I/O device coherency.
SRAM Bus that occur with byte and word accesses.
longwords with one Microengine command.
bit operations within the instruction (Push, Pop, Bit Test and Set, CAM operations,
Lock/Unlock, etc.).
®
IXP1200 Network Processor Family Hardware Reference Manual for details on
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O),
Intel
®
IXP1200 Network Processor
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