GCIXP1200GC Intel, GCIXP1200GC Datasheet - Page 24

• Manufacturer Part Number: GCIXP1200GC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839429

Intel
5.6.1
5.6.2
5.6.3
5.6.4
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IXP1200 Network Processor
Hardware Initiated Reset
The IXP1200 provides the RESET_IN# pin so that an external device can reset the IXP1200.
Asserting this pin resets the internal functions and generates an external reset via the
RESET_OUT# pin.
Upon power-up, RESET_IN# must remain asserted for 150 ms after VDD and VDDX are stable to
properly reset the IXP1200 and ensure that the PXTAL clock input and PLL Clock generator are
stable.
While RESET_IN# is asserted, the processor is held reset. When RESET_IN# is released, the
StrongARM* processor begins execution from SRAM address 0 after 512 PXTAL cycles. If
RESET_IN# is asserted while the StrongARM* core is executing, the current instruction
terminated abnormally and the on-chip caches, MMU, and write buffer are disabled.
The RESET_OUT# signal remains asserted until deasserted by the StrongARM* core. The
StrongARM* core deasserts the signal by writing bit 15 of the IXP1200_RESET register.
Software Initiated Reset
The StrongARM* core or an external PCI Bus master can reset specific functions in the IXP1200
by writing to the IXP1200_RESET register. In most cases, only the individual Microengines are
reset and the external RESET_OUT# pin will be asserted via this register. The ability to reset the
other functions is provided for debugging. The SRAM Unit is always reset when the StrongARM*
core is reset. To ensure a proper reset, the StrongARM* core and the SRAM Unit are held in reset
for 140 system clock cycles after RESET_IN# is deasserted. The other functions that can be reset
via the IXP1200_RESET register are properly reset when consecutive writes are performed to
assert and deassert the reset.
PCI Initiated Reset
The IXP1200 can be reset by an external PCI Bus master when the IXP1200 is not the PCI Central
Function and arbiter device (PCI_CFG[1:0] = 00) and PCI_RST# is an input. The entire IXP1200
is reset during a PCI Initiated Reset. When the IXP1200 is assigned as the PCI Central Function
and arbiter device (PCI_CFG[1:0] = 11), the IXP1200 drives PCI_RST# as an output to the other
devices on the PCI Bus.
Watchdog Timer Initiated Reset
The IXP1200 provides a watchdog timer that can reset the StrongARM* core. The StrongARM*
core should be programmed to reset the watchdog timer periodically to ensure that the timer does
not expire. If the watchdog timer expires, it is assumed the StrongARM* core has ceased executing
instructions properly. The reset generated by the Watchdog Timer will reset each of the functions in
the IXP1200.
Datasheet