GCIXP1200GC Intel, GCIXP1200GC Datasheet - Page 18

• Manufacturer Part Number: GCIXP1200GC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839429

Intel
5.4.4
18
Figure 4. SRAM Unit Block Diagram
®
IXP1200 Network Processor
SRAM Unit
The IXP1200 provides an SRAM Unit for very high bandwidth memory for storage of lookup
tables and other data for the packet processing Microengines. The SRAM Unit controls the SRAM
(up to 8 Mbytes), BootROM (up to 8 Mbytes) for booting, and 2 Mbytes of SlowPort address space
for peripheral device access. The I/O signal timing is determined by internal address decodes and
configuration registers for the BootROM and SlowPort address regions. The SRAM Unit includes
an 8 entry Push/Pop register list for fast queue operations, bit test, set and clear instructions for
atomic bit operations, and an 8 entry CAM for Read Locks.
The SRAM interface operates at one-half the IXP1200 core frequency (0.5 * F
The SRAM Unit supports both Pipelined Burst Double Cycle Deselect (DCD) and Flowthru
SRAM types. Other SSRAM devices, including single cycle deselect, are not supported. The bus is
also used to attach BootROM and can be used to interface other peripheral devices such as custom
interface logic or MAC management ports. The SRAM interface provides three separate timing
domains for the three device types: SRAM, BootROM, and Peripheral (also referred to as SlowPort
access).
BootROM devices may be either 32 bits or 16 bits in width. This is determined by GPIO[3] during
reset. When 16-bit BootROM devices are used, the maximum BootROM address space is reduced
from 8 Mbytes to 4 Mbytes.
Figure 4
The SRAM Bus consists of 19 address bits, 32 data bits, 4 chip enable bits, 8 buffer and read/write
control signals, a synchronous output clock (SCLK) running at one-half the IXP1200 core
frequency, and a synchronous input clock (SCLKIN). When using Flowthru SRAM types, it is
recommended to route the SCLK signal from the SRAMs back to the SCLKIN input. Routing this
* StrongARM is a registered trademark of ARM Limited.
** ARM architecture compatible
Pipelined-
BootROM
Flowthru
32KB to
DCD or
256KB
SRAM
8 MB
8MB
to
details the major components of the SRAM Unit.
Peripheral
CPU port)
(i.e., MAC
Device
RD/WR/EN
Signals
Data[31:0]
SCLK
Addr[18:0]
Buffer
Interface
SRAM
Pin
data
addr
& Address
Command
Generator
Decoder
Microengine Data [63:0]
Machine & Registers
Service Priority
(Arbitration)
AMBA Data
Memory/
FIFO
Microengine Address
& Command Queues
AMBA Address
(High Priority, Read,
Rd/Wr Queue
Readlock Fail
and Order)
AMBA Bus
Interface
Logic
core
).
(from
StrongARM
Core)
AMBA[31:0]
Microengine
Commands &
Addresses
Datasheet
A7014-02
®
*