GCIXP1200GC Intel, GCIXP1200GC Datasheet - Page 17

• Manufacturer Part Number: GCIXP1200GC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839429

5.4.2
5.4.3
Datasheet
Table 5. SDRAM Configurations
IXP1200 then updates only the bytes that were enabled and writes the entire quadword of data back
to SDRAM memory. (Note that the bytes do not have to be consecutive.) These three steps are
performed automatically.
SDRAM Bus Access Behavior
SDRAM Configurations
128 Mbytes
128 Mbytes
256 Mbytes
16 Mbytes
32 Mbytes
64 Mbytes
32 Mbytes
64 Mbytes
64 Mbytes
•
•
•
•
8 Mbytes
Memory
Total
The number of quadwords transferred by the SDRAM Unit is determined by the requesting
interface (StrongARM* core, Microengine, or PCI). The SDRAM Unit may reorder SDRAM
accesses for best performance.
Accesses are always quadword (64-bit) cycles on the SDRAM Bus.
Accesses from the StrongARM* core.
Accesses from the Microengines.
— Byte, word, and longword accesses generated from the StrongARM* core result in
— Consecutive longword writes over the AMBA Bus to the same quadword address are
— Read accesses using the Prefetch Memory address space allow the SDRAM Unit to
— The sdram microinstruction defines the number of 64-bit accesses to make, with up to 16
— Only quadword accesses are supported. Less than 8 bytes can be written when using the
Read-Modify-Write cycles to SDRAM space.
buffered and aggregated into quadword writes to SDRAM.
prefetch quadword data to be supplied to the AMBA Bus using 32-bit burst cycles.
quadwords with one instruction.
byte mask within an instruction, but result in Read-Modify-Write cycles.
# of Chips
4
8
4
8
4
8
4
8
4
8
128 Mbit
128 Mbit
256 Mbit
256 Mbit
16 Mbit
16 Mbit
64 Mbit
64 Mbit
64 Mbit
64 Mbit
DRAM
Size
Configuration
512 K x 16-bit
2 M x 16-bit
1 M x 16-bit
2 M x 16-bit
4 M x 16-bit
(per bank)
1 M x 8-bit
4 M x 8-bit
2 M x 8-bit
4 M x 8-bit
8 M x 8-bit
Internal
Banks
2
2
2
2
4
4
4
4
4
4
Intel
®
Bank Bits
IXP1200 Network Processor
1
1
1
1
2
2
2
2
2
2
RAS Bits
13
13
12
12
11
11
12
12
13
13
CAS Bits
10
10
8
9
8
9
8
9
9
9
17