GCIXP1200GC Intel, GCIXP1200GC Datasheet - Page 15

• Manufacturer Part Number: GCIXP1200GC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839429

5.3.1.1
5.4
Datasheet
In both 32-bit and 64-bit modes, all of the associated FBE# signals (FBE#[7:4] in 32-bit mode and
FBE#[7:0] for 64-bit mode) are driven low on a transmit. The last bus transfer, identified by the
assertion of EOP/EOP_RX in 64-bit mode or by TK_REQ_IN/EOP_TX in 32-bit mode, indicates
the number of valid bytes of this last transfer by driving only the valid FBE# signals.
Similarly for receive cycles, in both 32-bit and 64-bit modes, all associated FBE# signals must be
driven low by the peripheral or MAC device. The FBE# signals must identify the number of valid
bytes on the last transfer driven with EOP/EOP_RX. The IXP1200 uses this information to update
the RCV_CTL register’s Valid Bytes field. Driving fewer than the four or eight FBE#s, except for
the last transfer with EOP/EOP_RX, may cause undefined behavior.
Reset and Idle Bus Considerations
While the IXP1200 is in reset, or when the IX Bus is idle for at least 4 FCLK cycles and no bus
requests are pending, the IXP1200 drives the pins listed below. This is done so that the bus is not
left in a high-Z state for a prolonged period of time. This allows the designer to avoid the use of
keeper resistors on the pins to maintain valid levels.
FDAT[63:0]
FBE#[7:0]
FPS[2:0]
TXASIS/TXERR
RDYBUS[7:0]
RDYCTL#[3:0]
RDYCTL#[4]/FC_EN1#/RXPEN#
EOP/EOP_RX
SOP/SOP_RX
TK_REQ_IN/EOP_TX
TK_REQ_OUT/SOP_TX
RXFAIL
In shared IX Bus mode, pullups should be used on PORTCTL#[3:0], FPS[2:0], and
TXASIS/TXERR to maintain valid logic levels during bus exchanges.
In configurations where two IXP1200s are in Shared IX Bus Mode, the IXP1200s must be reset
synchronously, preferably with the same signal driving RESET_IN#. During reset, the IXP1200s
drive the pins listed above to identical logic states thereby avoiding logic state contention. If the
two devices are not reset synchronously, bus contention could result if one of the devices is held in
reset while the alternate device assumes the role of initial IX Bus owner and begins driving
transactions. This would result in obvious bus malfunction, and over time could affect device
reliability due to resulting high current conditions in the device.
SDRAM and SRAM Units
The IXP1200 supports two high performance memory units. The SRAM Unit provides fast
memory that can be used to store look-up tables. The SDRAM Unit provides lower cost memory
for forwarding information and transmit queues. Both units contain features that improve memory
bandwidth utilization.
Intel
®
IXP1200 Network Processor
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