GCIXP1200GC Intel, GCIXP1200GC Datasheet - Page 56

• Manufacturer Part Number: GCIXP1200GC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839429

Intel
56
Table 25. 64-Bit Bidirectional IX Bus, 3+ MAC Mode
®
IXP1200 Network Processor
(Shared IX Bus Operation Only in This Mode)
GPIO[3:1]
GPIO[0]/FC_EN0#/
TXPEN
RDYCTL#[4:0]
RDYBUS[7:0]
PORTCTL#[3:0]
FPS[2:0]
SOP/SOP_RX
TK_REQ_OUT/
SOP_TX
EOP/EOP_RX
TK_REQ_IN/EOP_TX
TK_IN
TK_OUT
RXFAIL
TXASIS/TXERR
Signal
Active High input/output assigned to StrongARM* core not used for MAC interface.
Active High, output assigned to StrongARM* core not used for MAC interface.
Output, 5 bits encoded for Transmit/Receive ready flags, flow-control, and
inter-chip communication in shared IX Bus mode.
Shared IX Bus mode, Initial Ready Bus master drives RDYCTL#[4:0] and Ready
Bus slave snoops.
Active High, input/output, Transmit or Receive Ready flags, flow control mask data,
and inter-processor communication in shared IX Bus mode.
Active Low, output, 4 bits encoded for transmit and receive commands and device
selects.
Shared IX Bus mode - Tri-stated when the IXP1200 does not own the IX Bus.
Active High, output, port select.
Shared IX Bus mode - Tri-stated when the IXP1200 does not own the IX Bus.
Active High, input/output, Start of Packet indication. SOP/SOP_RX is an output
during transmit according to values programmed in the TFIFO control field. Is an
input during receives indicating Receive Start of Packet from MAC.
Shared IX Bus mode - Tri-stated when the IXP1200 does not own the IX Bus.
Active High, output.
Single chip mode - not used, no connect.
Shared IX Bus mode - IX Bus Request.
Active High, input/output, End of Packet indication. EOP/EOP_RX is an output
during transmit according to values programmed in the TFIFO control field. Is an
input during receives indicating Receive End of Packet from MAC.
Shared IX Bus mode - Tri-stated when the IXP1200 does not own the IX Bus.
Active High, input/output.
Single chip mode - output, not used, terminate through 10 KOhms to VDDX.
Shared IX Bus mode - input, IX Bus Request pending.
Input in Shared IX Bus mode.
Single chip mode - pullup through 10 KOhms to VDDX.
Shared IX Bus mode - Token_Input, enables IX Bus ownership when a high-to-low
transition is detected. At reset, pull down through 10 KOhms to GND to tell the
IXP1200 that it does not own the IX Bus, pull up through 10 KOhms to VDDX to set
as initial IX Bus owner.
Active High, output.
Single chip mode - output, not used, no connect.
Shared IX Bus mode - Token_Output. When high, indicates this IXP1200 owns the
IX Bus.
Active High, input/output.
Input - Receive Error input.
Output - driven low during transmit and when bus maintains a No-Select state.
Shared IX Bus mode - Tri-stated when the IXP1200 does not own the IX Bus.
Active High, output. TXASIS/TXERR states are output according to values
programmed in the TFIFO Control field. TXASIS state is output coincident with
SOP/SOP_RX signal, TXERR state is output coincident with EOP/EOP_RX signal.
Shared IX Bus mode - Tri-stated when the IXP1200 does not own the IX Bus.
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