GCIXP1200GC Intel, GCIXP1200GC Datasheet - Page 19

• Manufacturer Part Number: GCIXP1200GC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839429

5.4.4.1
Datasheet
Note: Other SSRAM devices, including single cycle deselect, are not supported.
trace identically to the DQ data signals will skew the SCLKIN slightly to track the return data trace
propagation delay. When using Pipelined/DCD SRAMs, the SCLKIN input is not used and may be
held inactive with a pulldown to GND to save power.
The SRAM Unit receives memory requests from seven sources: the StrongARM* core and each of
the six Microengines. Refer to the IXP1200 Hardware Reference Manual for details on the
prioritization and queues provided for servicing these requests.
The IXP1200 supports the use of an optional asynchronous ready input for flexibility in interfacing
memory-mapped I/O devices to the SRAM Slowport region. This will allow the I/O device to add
wait-states to IXP1200 I/O accesses. This function is supported on the HIGH_EN#/RDY# pin. An
I/O device must drive HIGH_EN#/RDY# with a wired-OR open drain buffer configuration, and
only drive the pin when the I/O device is selected.
To use the RDY# pin function, it must be enabled by setting SRAM_CSR[19]=1. The RDY# Pause
State Value field located in register SRAM_SLOW_CONFIG[23:16] must be programmed with
the state value at which you choose to pause the internal wait-state logic. This pause state relates to
the other timing parameters programmed into the SRAM_SLOW_CONFIG and
SRAM_SLOWPORT_CONFIG register fields. See
SCC value is the total number of core clocks for the I/O cycle, and the SRWA, SCEA, SRWD, and
SCED values specify the RD/WR and Chip Enable signal assert and deassert times. When the I/O
cycles begins, the SCC value is loaded into the internal state counter and is decremented on each
core clock tick (twice the SCLK frequency). When the state counter reaches the RDY# Pause State
Value, it will remain in that state until the HIGH_EN#/RDY# pin is sampled LOW, allowing the
state counter to resume its decrement operation. The HIGH_EN#/RDY# must be driven for at least
two SCLK periods to be sampled properly by the IXP1200.
The RDY# Pause State must also occur at a minimum of 5 core clock periods prior to the SRWD
state to be recognized. A RDY# Pause State value of SRWD+5 (Decimal 10, Hexidecimal A) is
used in this example.
In this example, 6 additional core clock “wait-states” are inserted. If the RDY# input is
synchronous to SCLK and it meets the specified setup and hold times, the resulting number of wait
states will be predictable. However, if the RDY# input is asynchronous to SCLK, the number of
wait-states the IXP1200 inserts could vary by +/- 2 core clock periods.
SRAM Types Supported
Pipeline Burst DCD (double cycle deselect) type: tKQmax=4.2 ns, 3.3 V.
Flowthru type: tKQmax= 9 ns, 3.3 V.
Figure 73
Intel
which illustrates this example. The
®
IXP1200 Network Processor
19