GCIXP1200GC Intel, GCIXP1200GC Datasheet - Page 11

• Manufacturer Part Number: GCIXP1200GC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839429

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Datasheet
Introduction
Intel has created a new architecture, the IXP1200 Network Processor, to address the requirements
of today’s network equipment designers. The network processor is a fully programmable device
which has been specifically designed to handle the high speed data manipulation requirements of
networking equipment. It implements a symmetric array of six RISC data processors and a
StrongARM* processor, two memory interfaces, a PCI Interface, and an IX Bus Interface on a
single chip.
The IXP1200 architecture was defined as a loosely-coupled, hybrid parallel processor set,
integrating a StrongARM* processor with an array of RISC data engines. Maximum throughput
can be maintained by isolating them from memory accesses and the resulting latencies. This is
done by decoupling the functional units for the IX Bus, PCI Bus, SDRAM, and SRAM interfaces
from the execution pipelines through the extensive use of FIFO queues, and event task signaling.
Semaphore mechanisms and thread-level support are implemented in hardware, allowing for
zero-overhead context switching between threads executing on the Microengines.
Up to four thread-level tasks can be allocated per Microengine for a total of twenty-four threads in
a single IXP1200. Multiple IXP1200 devices can be aggregated in a serial or parallel fashion, or in
serial-parallel combinations to support diverse applications. Support chips from Intel can assist the
system designer in using the IXP1200 in these multiprocessor designs.
A full suite of software tools is available from Intel for Microengine code development, simulation,
and target hardware debugging. These tools can be used in conjunction with third-party
StrongARM* software tools and Realtime Operating Systems to build a complete embedded
solution.
Related Documents
Conventions
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Intel
Intel
Intel
Intel
Intel
ARM* V4.0 Architecture Reference
In all signal descriptions, an active low signal is indicated by a pound sign (#) in the signal
name.
In this and related IXP1200 documents, a word is equal to 16 bits, a longword is equal to 32
bits, and a quadword is equal to 64 bits. StrongARM* processor documents and the ARM*
V4.0 Architecture Reference typically refer to a word as being equal to 32 bits, and a halfword
as being equal to 16 bits.
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IXP1200 Network Processor Family Microcode Programmer’s Reference Manual
IXP1200 Network Processor Specification Update
IXP1200 Network Processor Family Development Tools User’s Guide
IXP1200 Network Processor Family Hardware Reference Manual
IXP1200 Network Processor Family Microcode Software Reference Manual
Intel
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IXP1200 Network Processor
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