MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 118

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

9.2 MSC Microcode Operation
In normal operation (without the MSC microcode), the QMC protocol allows specific bits
in an 8-bit time slot to be masked to create a single subchannel per SCC. A problem arises
when multiple subchannels are multiplexed within a single time slot as in GSM (global
system for mobile communications) where four 16-Kbps subchannels are multiplexed into
a single 64-Kbps channel over a 2.048-Mbps A bis link. A brute-force solution routes the
separate subchannels to different SCCs, consuming all four SCCs for the single TDM link
as shown in Figure 9-1. Each SCC filters out one of the four 2-bit subchannels in time slot 2
(TS2) using a unique mask located in its time slot assignment tables (TSATRx/TSATTx).
With the MSC microcode, subchannels can be regenerated using only one SCC.
The MSC microcode enables an 8-bit time slot to be split into multiple, bit-resolution
subchannels. The microcode applies user-defined masks in a time slot assignment table
entry to subdivide a given channel. Bit 11 of a table entry is now called the L bit to mark
the last subchannel of a given time slot. Figure 9-2 shows the MSC microcode solution to
the above GSM problem. Again in this example, time slot 2 contains four 2-bit channels,
but now the full time slot can be routed to a single SCC and split into subchannels within
the time slot assignment tables.
Figure 9-1. Two-Bit Subchannel Implementation without MSC Microcode
SCC1
Masking performed within each SCC to create 2-bit channels
TS0
Freescale Semiconductor, Inc.
For More Information On This Product,
TS1
SCC2
Go to: www.freescale.com
QMC Supplement
TS2
SCC3
SCC4
8 Bits
TS31