MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 87

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

#—TSATRx & TSATTx are mapped to an alternative SCC’s parameter RAM.
*—SPI is not available in these configurations due to memory conflict.
IMMR + 3D00
IMMR + 3D37
IMMR + 3D38
IMMR + 3D7F
IMMR + 3D80
IMMR + 3DAF
IMMR + 3DB0
IMMR + 3DBF
IMMR + 3DC0
IMMR + 3DFF
IMMR + 3D00
IMMR + 3DA3
IMMR + 3DA4
IMMR + 3DAF
IMMR + 3DB0
IMMR + 3DBF
IMMR + 3DC0
IMMR + 3DFF
Figure 5-13. MPC860MH SCC2 Parameter RAM Usage
Transparent
Transparent Regs
= 56 Bytes
Ethernet Regs
= 164 Bytes
Ethernet
Locations used
Freescale Semiconductor, Inc.
for SCC registers
Free Area
= 72Bytes
IDMA2 Regs
= 64Bytes
SPI Regs
= 48Bytes
Timers Regs
= 16 Bytes
Free Area
= 12Bytes
IDMA2 Regs
= 64Bytes
Timers Regs
= 16 Bytes
For More Information On This Product,
*
IMMR + 3D00
IMMR + 3DAB
IMMR + 3DAC
IMMR + 3DAF
IMMR + 3DB0
IMMR + 3DBF
IMMR + 3DC0
IMMR + 3DFF
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IMMR + 3D00
IMMR + 3D5B
IMMR + 3D5C
IMMR + 3D7F
IMMR + 3D80
IMMR + 3DAF
IMMR + 3DB0
IMMR + 3DBF
IMMR + 3DC0
IMMR + 3DFF
Chapter 5. Buffer Descriptors
Free Area
= 36 Bytes
HDLC Regs
= 92 Bytes
QMC Regs
= 172 Bytes
Timers Regs
= 16 Bytes
IDMA2 Regs
= 64Bytes
Free Area
= 4 Bytes
IDMA2 Regs
= 64Bytes
Timers Regs
= 16 Bytes
HDLC
SPI Regs
= 48Bytes
QMC
Locations free
for BD
*
IMMR + 3D00
IMMR + 3D1F
IMMR + 3D20
IMMR + 3D9F
IMMR + 3DA0
IMMR + 3DAB
IMMR + 3DAC
IMMR + 3DAF
IMMR + 3DB0
IMMR + 3DBF
IMMR + 3DC0
IMMR + 3DFF
IMMR + 3D65
IMMR + 3D66
IMMR + 3D7F
IMMR + 3D80
IMMR + 3DAF
IMMR + 3DB0
IMMR + 3DBF
IMMR + 3DC0
IMMR + 3DFF
IMMR + 3D00
QMC on
Multiple SCCs
QMC Regs
=12 Bytes
UART Regs
= 102 Bytes
QMC Regs
= 32 Bytes
Timers Regs
= 16 Bytes
IDMA2 Regs
= 64Bytes
Free Area
= 128 Bytes
Free Area
= 4 Bytes
IDMA2 Regs
= 64Bytes
Timers Regs
= 16 Bytes
UART
Free Area
= 26 Bytes
SPI Regs
= 48Bytes
Locations used
for secondary
registers
*#