MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 98

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Step 16. Initialize channel-specific parameters for HDLC or transparent mode as follows.
For more information on HDLC, see Section 2.4.1, “Channel-Specific HDLC Parameters,”
and for transparent mode, see Section 2.4.2, “Channel-Specific Transparent Parameters.”
Repeat for each of the enabled channels.
• TBASE: TxBD descriptors base address. Initialize to location of first TxBD =
• TSTATE: Tx internal state. For the MH360, this is typically 0x3800
• RSTATE: Rx internal state. For the MH360, this is typically 0x3900
• ZISTATE: zero insertion should be initialized to 0x0000
• ZDSTATE: zero deletion machine state should be initialized to 0x1800
• INTMSK: channel’s interrupt mask flags. Bits should be set to enable the
MCBASE+TBASE.
RBASE: RxBD descriptors base address. Initialize to location of first RxBD =
MCBASE+RBASE.
ch[0].RBASE = 0;
ch[0].TBASE = 8;
ch[1].RBASE = 0x10;
ch[1].TBASE = 0x18;
ch[2].RBASE = 0x20;
ch[2].TBASE = 0x28;
ch[3].RBASE = 0x30;
ch[3].TBASE = 0x38;
Copy RBASE to RBPTR (Rx buffer descriptor pointer) and TBASE to TBPTR (Tx
buffer descriptor pointer).
ch[x].TBPTR = ch[x].TBASE;
ch[x].RBPTR = ch[x].RBASE;
860MH, this is typically 0x3000
ch[x].TSTATE = 0x3800_0000;
ch[x].TSTATE = 0x3000_0000;
860MH, this is typically 0x3100
ch[x].RSTATE = 0x3900_0000;
ch[x].RSTATE = 0x3100_0000;
ch[x].ZISTATE = 0x100;
transparent mode or 0x0000
ch[x].ZDSTATE = 0x80;
corresponding interrupts.
ch[x].INTMSK = 0xA;
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0080 for HDLC.
QMC Supplement
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_
0000.
0000.
/* locate CH0 RxBDS at 0 */
/* locate CH0 TxBDS at 8 */
/* locate CH1 RxBDS 0x10 */
/* locate CH1 TxBDS 0x18 */
/* locate CH2 RxBDS 0x20 */
/* locate CH2 TxBDS 0x28 */
/* locate CH3 RxBDS 0x30 */
/* locate CH3 TXBDS 0x38 */
/* setting for MH360 */
/* setting for 860MH */
/* setting for MH360 */
/* setting for 860MH */
/* set ZDZTATE for HDLC */
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0100.
_
_
0000. For the
0000. For the
_
0080 for