MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 55

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Take the example of a superchannel of several time slots:
The algorithm for the receiver byte in decimal is:
The algorithm for the transmit byte in decimal is:
The result from these calculations is a decimal value programmed into TRNSYNC.
The following nine cases in Figure 2-14, named C1 to C9, show different scenarios ranging
from a single time slot per logical channel to a superchannel using several time slots. In this
application, 24 time slots are routed to this SCC from the SI RAM. After time slot 23, the
frame starts with 0 again. The arrow in all the figures illustrates the starting position.
C1 is for a single byte in TS7, so TSn = 7
Rx Byte:
As x = 0, TSn + x = TSn = 7, so
TX Byte:
C2 is a single byte in TS23, so TSn = 23. Note that time slot after 23 is 0, so in the
calculations below 23 + 1 = 0.
Rx Byte:
As x = 0, TSn + x = TSn = 23, so
TX Byte:
C3 is a 2-byte pattern TS7, TS8, so TSn = 7
Rx Byte:
As x = 1, TSn + x = 8, so
TX Byte:
TSn, TSn + 1, TSn + 2 ....... TSn + x
(TSn + 1) * 2
(TSn + x + 1) * 2
Note that TSn is not necessarily the first time slot in the frame.
For example, if a superchannel is produced from TS2, TS4, and
TS6, the message may be arranged with TS4 holding the first
byte, then TS6, and the final byte held in TS2 of the following
frame.
(7+1) * 2 = 16
(7 + 1) * 2 = 16
(23 + 1) * 2 = 0
(23 + 1) * 2 = 0
(7 + 1) * 2 = 16
(8 + 1) * 2 = 18
Freescale Semiconductor, Inc.
For More Information On This Product,
Chapter 2. QMC Memory Organization
Go to: www.freescale.com
NOTE