MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 48

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

RESET:
Reset:
2.4.1.3 INTMSK—Interrupt Mask (HDLC)
Each event defined in the interrupt circular queue entry maps directly to a bit in INTMSK
as shown in Figure 2-9. There is one mask bit for each event—NID (bit 2), IDL (bit 3),
MRF (bit 10), UN (bit 11), RXF (bit 12), BSY (bit 13), TXB (bit 14) and RXB (bit 15). Bits
that do not map to an event are reserved. Reserved bits must be set to zero. Refer to
Chapter 4, “QMC Exceptions,” for more detail.
This register is initialized by the host prior to operation.
Interrupt Table Entry:
INTMSK:
0–1
2
3
4
5–7
Field
RESERVED
0
V
0
0
0
• 0 = No interrupt request is generated and no new entry is written in the circular
• 1 = Interrupts are enabled.
Note: For the 68360, the bit numbering is reversed. See Appendix A for more information.
interrupt table.
W
1
0
—
—
MOT
—
AT[1–3]
1
0
Name
NID
2
0
INTERRUPT
2
0
Table 2-7. TSTATE Field Descriptions for 860MH (HDLC)
MASK
0
1
Motorola/Intel bit
0 = The bus format is Intel format (little-endian).
1 = The system bus is considered to be organized in Motorola format (big-endian).
0
Address type—This field contains the address type for the transmitter DMA channel for data
buffers in external memory (transmit buffers). Address types are needed by the memory
controller to decode a correct memory cycle and activate the correct handshaking.
Figure 2-9. INTMSK and Interrupt Table Entry (HDLC)
IDL
Freescale Semiconductor, Inc.
3
0
3
0
For More Information On This Product,
—
4
0
4
0
5
0
Go to: www.freescale.com
5
0
6
0
CHANNEL NUMBER
RESERVED
6
0
QMC Supplement
7
0
7
0
8
0
Description
8
0
9
0
9
0
MRF
10
0
10
0
UN
11
0
11
0
INTERRUPT MASK BITS
RXF
12
0
12
0
BSY
13
0
13
0
TXB
14
0
14
0
RXB
15
0
15
0