MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 73

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Figure 5-2 shows how non-octet alignment is reported and how data is stored. The two
diagrams on the left show the reception of a single-buffer, 12-byte frame including the
CRC. In the top case, the reception is correctly octet-aligned and the frame length indicates
12 bytes.
11
12
13
14–15
16–31
32–63
Field
Table 5-1. Receive Buffer Descriptor (RxBD) Field Descriptions (Continued)
Name
NO
AB
CR
—
DL
RxBP
Rx non-octet-aligned frame (HDLC mode only)—A frame that contained a number of bits not
exactly divisible by eight was received. NO = 1 for any type of nonalignment regardless of frame
length. The shortest frame that can be detected is of type Flag-Bit-Flag. This causes the buffer to
be closed with the NO error indicated.
Figure 5-2 shows how the non-octet alignment is reported and where data can be found.
Rx abort sequence—A minimum of seven consecutive ones was received during frame
reception. Abort is not detected between frames. The sequence ...closing-flag, data, CRC, flag,
AB, flag, data, opening-flag... does not cause an abort error. If the abort is long enough to be an
idle, an idle line interrupt may be generated. An abort within the frame is not reported by a unique
interrupt but rather with an RXF interrupt; the user has to examine the buffer descriptor.
Rx CRC error—This frame contains a CRC error. The received CRC bytes are always written to
the receive buffer.
—
Data length—the number of octets written by the CPM into this buffer descriptor’s data buffer. It is
written by the CPM once when the buffer descriptor is closed.
When this buffer descriptor is the last buffer descriptor of a frame (L = 1), the data length equals
the total number of octets in the frame (including the two- or four-byte CRC).
Note: The amount of memory allocated for this buffer should be greater than or equal to the
contents of the maximum receive buffer length register (MRBLR + 4).
Rx buffer pointer—The receive buffer pointer, which always points to the first location of the
associated data buffer, may reside in either internal or external memory. The Rx buffer pointer
must be divisible by 4.
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Chapter 5. Buffer Descriptors
Description