MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 44

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

2.4 Channel-Specific Parameters
The channel-specific parameters are located in the lower part of the dual-ported RAM. Each
channel occupies 64 bytes of parameters. Physical time slots can be matched to logical
channels in several combinations. Unused logical channels leave a hole in the channel-
specific parameters that can be used for buffer descriptors for the other SCCs.
The channel-specific area determines the operating mode—HDLC or transparent. Several
entries take on different meanings depending on the protocol chosen.
2.4.1 Channel-Specific HDLC Parameters
Table 2-4 describes the channel-specific HDLC parameters. Boldfaced parameters must be
initialized by the user.
00
02
04
08
0C
0E
10
14
18
1C
1E
20
Offset
TBASE
CHAMR
TSTATE
—
TBPTR
—
TUPACK
ZISTATE
TCRC
INTMSK
BDFlags
RBASE
Name
Freescale Semiconductor, Inc.
Width
16
16
32
32
16
16
32
32
32
16
16
16
(Bits)
Table 2-4. Channel-Specific HDLC Parameters
For More Information On This Product,
Tx buffer descriptor base address—Offset of the channel’s transmit buffer
descriptor table relative to MCBASE, host-initialized. See Figure 2-2.
Channel mode register. See Section 2.4.1.1, “CHAMR—Channel Mode Register
(HDLC).”
Tx internal state —TSTATE defines the internal Tx state.
Host-initialized to 0x3800
Host-initialized to 0x3000
Initialize before enabling the channel. See Section 2.4.1.2, “TSTATE—Tx Internal
State (HDLC).”
Tx internal data pointer—Points to current absolute address of channel.
Tx buffer descriptor pointer (host-initialized to TBASE before enabling the channel
or after a fatal error before reinitializing the channel again)—Offset of current BD
relative to MCBASE. See Table 2-1. MCBASE + TBPTR gives the address for the
BD in use.
Tx internal byte count—Number of remaining bytes
(Tx Temp) Unpack 4 bytes from 1 long word
Zero-insertion state (host-initialized to 0x0000
operation)—Contains the previous state of the zero-insertion state machine.
Temp transmit CRC—Temp value of CRC calculation result
Channel’s interrupt mask flags—See Section 2.4.1.3, “INTMSK—Interrupt Mask
(HDLC).”
Temp
Rx buffer descriptor offset (host-initialized)— Defines the offset of the channel’s
receive BD table relative to MCBASE (64-Kbyte table). See Figure 2-2.
Go to: www.freescale.com
QMC Supplement
_
_
0000—FC = 8, Motorola mode for MH360.
0000— AT = 0, Motorola mode for 860MH.
Description
_
0100 for HDLC or transparent