DS21FF42 Maxim Integrated Products, DS21FF42 Datasheet - Page 21

• Manufacturer Part Number: DS21FF42
• Description: IC FRAMER T1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF42

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

A 4 kHz or 2 kHz (ZBTSI) clock for the RLINK output. This signal is not bonded out in the
DS21FF42/DS21FT42.
A 192 kHz clock which pulses high during the LSB of each channel. Synchronous with RCLK when the
receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is
enabled. Useful for parallel to serial conversion of channel data. This function is available when FMS =
1 (DS21Q41 emulation). This signal is not bonded out in the DS21FF42/DS21FT42.
A user programmable output that can be forced high or low during any of the 24 T1 channels.
Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK
when the receive side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all T1 channels are used such as Fractional T1, 384K bps service,
768K bps, or ISDN–PRI. Also useful for locating individual channels in drop–and–insert applications,
for external per–channel loopback, and for per–channel conditioning. See Section 16 for details.
Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is
disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.
An extracted pulse, one RCLK wide, is output at this pin which identifies either frame (RCR2.4 = 0) or
multiframe (RCR2.4 = 1) boundaries. If set to output frame boundaries then via RCR2.5, RSYNC can
also be set to output double–wide pulses on signaling frames. If the receive side elastic store is enabled
via CCR1.2, then this pin can be enabled to be an input via RCR2.3 at which a frame or multiframe
boundary pulse is applied. See Section 24 for details.
An extracted 8 kHz pulse, one RCLK wide, is output at this pin which identifies frame boundaries. This
signal is not bonded out in the DS21FF42/DS21FT42.
Signal Name:
Signal Description:
Signal Type:
Signal Name:
Signal Description:
Signal Type:
Signal Name:
Signal Description:
Signal Type:
Signal Name:
Signal Description:
Signal Type:
Signal Name:
Signal Description:
Signal Type:
Signal Name:
Signal Description:
Signal Type:
RLCLK
Receive Link Clock
Output
RCHCLK
Receive Channel Clock
Output
RCHBLK
Receive Channel Block
Output
RSER
Receive Serial Data
Output
RSYNC
Receive Sync
Input /Output
RFSYNC
Receive Frame Sync
Output
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