DS21FF42 Maxim Integrated Products, DS21FF42 Datasheet - Page 81

• Manufacturer Part Number: DS21FF42
• Description: IC FRAMER T1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF42

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS21FT42/DS21FF42
determining which channels are to have Bit 7 stuffing performed. If the TCR2.0 and TCR1.3 bits are set
to one, then all 24 T1 channels will have Bit 7 stuffing performed on them regardless of how the TTR
registers are programmed. In this manner, the TTR registers are only affecting which channels are to
have robbed bit signaling inserted into them. Please see Figure 24-15 for more details.
21.
INTERLEAVED PCM BUS OPERATION
In many architectures, the outputs of individual framers are combined into higher speed serial buses to
simplify transport across the system. The DS21Q42 can be configured to allow each framer’s data and
signaling busses to be multiplexed into higher speed data and signaling busses eliminating external
hardware saving board space and cost.
The interleaved PCM bus option supports two bus speeds and interleave modes. The 4.096 MHz bus
speed allows two framers to share a common bus. The 8.192 MHz bus speed allows all four of the
DS21Q42’s framers to share a common bus. Framers can interleave their data either on byte or frame
boundaries. Framers that share a common bus must be configured through software and require several
device pins to be connected together externally (see figures 22-1 & 22-2). Each framer’s elastic stores
must be enabled and configured for 2.048 MHz operation. The signal RSYNC must be configured as an
input on each framer.
For all bus configurations, one framer will be configured as the master device and the remaining framers
on the shared bus will be configured as slave devices. Refer to the IBO register description below for
more detail. In the 4.096 MHz bus configuration there is one master and one slave per bus. Figure 22-1
shows the DS21Q42 configured to support two 4.096 MHz buses. Bus 1 consists of framers 0 and 1.
Bus 2 consists of framers 2 and 3. Framers 0 and 2 are programmed as master devices. Framers 1 and 3
are programmed as slave devices. In the 8.192 MHz bus configuration there is one master and three
slaves. Figure 22-2 shows the DS21Q42 configured to support a 8.192 MHz bus. Framers 0 is
programmed as the master device. Framers 1, 2 and 3 are programmed as slave devices. Consult timing
diagrams in section 24 for additional information.
When using the frame interleave mode, all framers that share an interleaved bus must have receive
signals (RPOS & RNEG) that are synchronous with each other. The received signals must originate
from the same clock reference. This restriction does not apply in the byte interleave mode.
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