DS21FF42 Maxim Integrated Products, DS21FF42 Datasheet - Page 53

• Manufacturer Part Number: DS21FF42
• Description: IC FRAMER T1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF42

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex)
[repeated here from section 10 for convenience]
(MSB)
RJC
RESALGN
TESALGN
SYMBOL
SYMBOL
RCM4
RCM3
RCM2
RCM1
RCM0
RJC
B6
B7
B8
RESALGN
POSITION
POSITION
TDS0M.2
TDS0M.1
TDS0M.0
CCR6.7
CCR6.6
CCR6.5
CCR6.4
CCR6.3
CCR6.2
CCR6.1
CCR6.0
TESALGN
NAME AND DESCRIPTION
NAME AND DESCRIPTION
Transmit DS0 Channel Bit 6.
Transmit DS0 Channel Bit 7.
Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last
bit to be transmitted).
Receive Japanese CRC6 Enable.
0 = use ANSI/AT&T/ITU CRC6 calculation (normal
operation)
1 = use Japanese standard JT–G704 CRC6 calculation
Receive Elastic Store Align. Setting this bit from a zero to a
one will force the receive elastic store’s write/read pointers to
a minim separation of half a frame. If pointer separation is
already greater than half a frame, setting this bit will have no
effect. Should be toggled after RSYSCLK has been applied
and is stable. Must be cleared and set again for a subsequent
align. See Section 17 for details.
Transmit Elastic Store Align. Setting this bit from a zero to
a one will force the transmit elastic store’s write/read pointers
to a minimum separation of half a frame. If pointer
separation is already greater than half a frame, setting this bit
will have no effect. Should be toggled after TSYSCLK has
been applied and is stable. Must be cleared and set again for
a subsequent align. See Section 17 for details.
Receive Channel Monitor Bit 4. MSB of a channel decode
that determines which receive channel data will appear in the
RDS0M register. See Section 13 for details.
Receive Channel Monitor Bit 3.
Receive Channel Monitor Bit 2.
Receive Channel Monitor Bit 1.
Receive Channel Monitor Bit 0. LSB of the channel
decode.
RCM4
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RCM3
RCM2
RCM1
RCM0
(LSB)