DS21FF42 Maxim Integrated Products, DS21FF42 Datasheet - Page 75

IC FRAMER T1 4X4 16CH 300-BGA

DS21FF42

Manufacturer Part Number
DS21FF42
Description
IC FRAMER T1 4X4 16CH 300-BGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS21FF42

Controller Type
T1 Framer
Interface
Parallel/Serial
Voltage - Supply
2.97 V ~ 3.63 V
Current - Supply
300mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
300-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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TDC2: TRANSMIT HDLC DS0 CONTROL REGISTER 2 (Address = 93 Hex)
19.2 LEGACY FDL SUPPORT
19.2.1 Overview
The DS21Q42 maintains the circuitry that existed in the previous generation of Dallas Semiconductor’s
single chip transceivers and quad framers. Section 19.2 covers the circuitry and operation of this legacy
functionality. In new applications, it is recommended that the HDLC controller and BOC controller
described in Section 19.1 be used. On the receive side, it is possible to have both the new HDLC/BOC
controller and the legacy hardware working at the same time. However this is not possible on the
transmit side since their can be only one source the of the FDL data internal to the device.
19.2.2 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit–by–bit into the Receive FDL
register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms (8 times 250 us). The
framer will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via
IMR2.4, the INT* pin will toggle low indicating that the buffer has filled and needs to be read. The user
has 2 ms to read this data before it is lost. If the byte in the RFDL matches either of the bytes
programmed into the RMTCH1 or RMTCH2 registers, then the SR2.2 bit will be set to a one and the
INT* pin will toggled low if enabled via IMR2.2. This feature allows an external microcontroller to
ignore the FDL or Fs pattern until an important event occurs.
The framer also contains a zero destuffer, which is controlled via the CCR2.0 bit. In both ANSI T1.403
and TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol
states that no more than 5 ones should be transmitted in a row so that the data does not resemble an
opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS21Q42
(MSB)
TDB8
SYMBOL
TDB8
TDB7
TDB6
TDB5
TDB4
TDB3
TDB2
TDB1
TDB7
POSITION
TDC2.7
TDC2.6
TDC2.5
TDC2.4
TDC2.3
TDC2.2
TDC2.1
TDC2.0
TDB6
NAME AND DESCRIPTION
DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to
stop this bit from being used.
DS0 Bit 7 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 6 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 5 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 4 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 3 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 2 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to
stop this bit from being used.
TDB5
75 of 114
TDB4
TDB3
TDB2
(LSB)
TDB1

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