DS21FF42 Maxim Integrated Products, DS21FF42 Datasheet - Page 68

• Manufacturer Part Number: DS21FF42
• Description: IC FRAMER T1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF42

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

HSR: HDLC STATUS REGISTER (Address = 01 Hex)
(MSB)
RBOC
SYMBOL
SYMBOL
TCRCD
RHALF
TEOM
RBOC
TABT
TZSD
THR
RPE
RPS
TFS
RPE
POSITION
POSITION
HCR.5
HCR.4
HCR.3
HCR.2
HCR.1
HCR.0
HSR.7
HSR.6
HSR.5
HSR.4
RPS
NAME AND DESCRIPTION
Transmit Flag/Idle Select.
0 = 7Eh
1 = FFh
Transmit HDLC/BOC Reset. A 0 to 1 transition will reset
both the HDLC controller and the transmit BOC circuitry.
Must be cleared and set again for a subsequent reset.
Transmit Abort. A 0 to 1 transition will cause the FIFO
contents to be dumped and one FEh abort to be sent followed
by 7Eh or FFh flags/idle until a new packet is initiated by
writing new data into the FIFO. Must be cleared and set
again for a subsequent abort to be sent.
Transmit End of Message. Should be set to a one just
before the last data byte of a HDLC packet is written into the
transmit FIFO at THFR. The HDLC controller will clear this
bit when the last byte has been transmitted.
Transmit Zero Stuffer Defeat. Overrides internal enable.
0 = enable the zero stuffer (normal operation)
1 = disable the zero stuffer
Transmit CRC Defeat.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
NAME AND DESCRIPTION
Receive BOC Detector Change of State. Set whenever the
BOC detector sees a change of state from a BOC Detected to
a No Valid Code seen or vice versa. The setting of this bit
prompt the user to read the RBOC register for details.
Receive Packet End. Set when the HDLC controller detects
either the finish of a valid message (i.e., CRC check
complete) or when the controller has experienced a message
fault such as a CRC checking error, or an overrun condition,
or an abort has been seen. The setting of this bit prompts the
user to read the RHIR register for details.
Receive Packet Start. Set when the HDLC controller
detects an opening byte. The setting of this bit prompts the
user to read the RHIR register for details.
Receive FIFO Half Full. Set when the receive 64–byte
FIFO fills beyond the half way point. The setting of this bit
prompts the user to read the RHIR register for details.
RHALF
68 of 114
RNE
THALF
TNF
TMEN
(LSB)
D