SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 149

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

Interrupt Status Register 0 (ISR0)
Access: read
Value after RESET: 00
All bits are reset when ISR0 is read. Additionally, RME and RPF are reset when the
corresponding interrupt vector is output.
Note: If bit IPC:VIS is set to ‘1’, interrupt statuses in ISR0 may be flagged although they
RME …
RFS …
RSC …
Semiconductor Group
ISR0
are masked via register IMR0. However, these masked interrupt statuses neither
generate an interrupt vector or a signal on INT, nor are visible in register GIS.
RME
7
Receive Message End
One complete message of length less than 32 bytes, or the last
part of a frame at most 32 bytes long including the status byte is
stored in the receive FIFO.
The complete message length can be determined reading the
RBCH, RBCL registers, the number of bytes currently stored in
RFIFO is given by RBC4 ... 0. Additional information is available
in the RSTA byte, stored in the RFIFO as the last byte of each
frame.
Receive Frame Start
This is an early receiver interrupt activated after the start of a valid
frame has been detected, i.e. after an address match (in operation
modes providing address recognition), or after the opening flag
(transparent mode 0) is detected, delayed by two bytes. After an
RFS interrupt, the contents of
• RHCR
• RAL1
• RSTA-bits 3 … 0
are valid and can be read by the CPU.
Receive Status Change (significant in auto-mode only)
A status change (receiver ready/receiver not ready) of the remote
station has been detected by receiving a RR/RNR supervisory
frame. The actual status can be read from the STAR register
(RRNR bit).
H
RFS
address: ch-A: 3A
RSC
ch-B: 7A
149
PCE
H
H
PLLA
Detailed Register Description
SAB 82532/SAF 82532
CDSC
RFO
HDLC Mode
RPF
07.96
0