SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 70

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

Semiconductor Group
6.2.2
If the receiver is enabled, received data is stored in RFIFO (the LSB is received first).
Moreover, the CD input may be used to control data reception. Character length, number
of stop bits and the optional parity bit are checked. Storage of parity bits can be disabled.
Errors are indicated via interrupts. Additionally, the character error status (framing and
parity) can optionally be stored in the RFIFO (refer to chapter 10.1.2).
Filling of the accessible part of RFIFO is controlled by
• a programmable threshold level
• detection of the programmable Termination Character (optional).
Additionally, the time-out condition as optional status information indicates that a certain
time (refer to register ISR0) has elapsed since the reception of the last character.
6.3
The selection of asynchronous or isochronous operation has no further influence on the
transmitter. The bit clock rate is solely a dividing factor for the selected clock source.
Transmission of the contents of XFIFO starts after the XF command is issued (the LSB
is sent out first). Further data is requested by interrupt (XPR) or DMA. The character
frame for each character, consisting of start bit, the character itself with defined
character length, optionally generated parity bit and stop bit(s) is assembled.
After finishing transmission (indicated by the ‘All Sent’ interrupt), IDLE (logical ‘1’) is
transmitted on TxD.
Additionally, the CTS signal may be used to control data transmission.
6.4
6.4.1
Break generation: On issuing the XBRK command (register DAFO), the TxD pin is
immediately forced to physical ‘0’ level with the first following clock edge, and released
with the first clock edge after this command has been reset.
Break detection: The ESCC2 recognizes the break condition upon receiving consecutive
(physical) ‘0’s for the defined character length, the optional parity and the selected
number of stop bits (‘zero’ character and framing error). The ‘zero’ character is not
pushed to RFIFO. If enabled, the BRK interrupt is generated.
The break condition will be present until a ‘1’ is received which is indicated by the ‘Break
Terminated’ interrupt (BRKT).
Storage of Data
Data Transmission
Special Features
Break Detection/Generation
70
Asynchronous Serial Mode
SAB 82532/SAF 82532
07.96