SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 82

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

Semiconductor Group
Clock Mode 1 (receive/transmit strobes)
Externally generated, but identical receive and transmit clocks are supplied via RxCLK.
In addition, a receive strobe can be connected via CD and a transmit strobe via TxCLK.
These strobe signals work on a per bit basis. The operating mode can be applied in time
division multiplex applications or for adjusting disparate transmit and receive data rates.
Note: In Extended Transparent Mode (HDLC/SDLC), the above mentioned strobe
Clock Mode 2 (receive clock from DPLL)
The BRG is driven by an external clock (RxCLK) and it delivers a reference clock of a
frequency equal to 16 times the nominal bit rate for the DPLL which in turn generates the
receive clock. Depending on the programming of the CCR2 register (bit SSEL), the
transmit clock will be either an external clock signal (TxCLK) or the clock delivered by
the BRG divided by 16. In the latter case, the transmit clock can be output via TxCLK.
Clock Mode 3 (receive and transmit clock from DPLL)
The BRG is fed with an externally generated clock via RxCLK. Depending on the value
of bit CCR2:SSEL the BRG supplies either the reference clock of frequency equal to 16
times the nominal bit rate for the DPLL, which generates both the receive and transmit
clock, or, the receive and transmit clock directly. This clock can be output via TxCLK.
Clock Mode 4 (OSC – direct)
The receive and transmit clocks are directly supplied by the OSC. In addition, this clock
can be output via TxCLK.
Clock Mode 5 (time-slots)
This operation mode has been designed for application in time-slot oriented PCM
systems.
Note: Clock mode 5 is only specified for versions SAB/SAF 82532 N-10 and
The received and transmit clock are common for each channel and must be supplied
externally via RxCLK pin. The ESCC2 receives and transmits only during certain
time-slots
– of programmable width (1 … 256 bit, via RCCR and XCCR registers), and
– of programmable location with respect to a frame synchronization signal (via CD pin).
One of up to 64 time-slots can be programmed independently for receive and transmit
direction via TSAR and TSAX registers, and an additional clock shift of 0 … 7 bits via
TSAR, TSAX and CCR2 register. Together with bits XCS0 and RCS0 (LSB of clock
signals provide byte synchronization (byte alignment).
SAB/SAF 82532 H-10, but not for versions SAB 82532 N and SAB 82532 H.
For correct operation only NRZ coding should be used.
82
Serial Interface (layer-1 functions)
SAB 82532/SAF 82532
07.96