SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 97

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

8.5
8.5.1
The ESCC2 provides two pins (RTS, CTS) per serial channel supporting the standard
RTS modem handshaking procedure for transmission control.
A transmit request will be indicated by outputting logical ‘0’ on the request-to-send output
(RTS). It is also possible to control the RTS output by software. After having received the
permission to transmit (CTS) the ESCC2 starts data transmission.
HDLC/SDLC and BISYNC: In the case where permission to transmit is withdrawn in the
course of transmission, the frame is aborted and IDLE is sent. After transmission is
enabled again by re-activation of CTS, and if the beginning of the frame is still available
in the ESCC2, the frame will be re-transmitted (self-recovery). However, if the
permission to transmit is withdrawn after the data in the first XFIFO pool has been
completely transmitted and the pool is released, the transmitter and the XFIFO are reset,
the RTS output is deactivated and an interrupt (XMR) is generated.
Note: For correct identification as to which frame is aborted and thus has to be repeated
ASYNC: In the case where permission to transmit is withdrawn, transmission of the
current character is completed. After that, IDLE is sent. After transmission is enabled
again by re-activation of CTS, the next available character is sent out.
Note: In the case where permission to transmit is not required, the CTS input can be
Additionally, any transition on the CTS input pin will generate an interrupt indicated via
the ISR1 register, if this function is enabled by setting the CSC bit in the IMR1 register.
Semiconductor Group
after an XMR interrupt has occurred, the contents of XFIFO have to be unique, i.e.
XFIFO should not contain data of more than one frame, which could happen if
transmission of a new frame is started by loading new data in XFIFO and issuing
a transmit command upon reception of XPR interrupt. For this purpose the All Sent
interrupt (ISR1: ALLS) instead of XPR has to be used to trigger the loading of data
(for the next frame) into XFIFO.
connected directly to
Modem Control Functions (RTS/CTS, CD)
RTS/CTS Handshaking
V
SS
.
97
Serial Interface (layer-1 functions)
SAB 82532/SAF 82532
07.96