SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 88

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

SAB 82532/SAF 82532
Serial Interface (layer-1 functions)
8.2
Clock Recovery (DPLL)
The ESCC2 offers the advantage of recovering the received clock from the received data
by means of internal DPLL circuitry, thus eliminating the need to transfer additional clock
information via the serial link. For this purpose, the DPLL is supplied with a ‘reference
clock’ from the BRG which is 16 times the nominal data clock rate (clock mode 2, 3a, 6,
7a). The transmit clock may be obtained by dividing the output of the BRG by a constant
factor of 16 (clock mode 2a, 6a; bit SSEL in CCR2 set) or also directly from the DPLL
(clock mode 3a, 7a).
The main task of the DPLL is to derive a receive clock and to adjust its phase to the
incoming data stream in order to enable optimal bit sampling.
The mechanism for clock recovery depends on the selected data encoding (refer to
chapter 8.4).
The following functions have been implemented to facilitate a fast and reliable
synchronization:
Interference Rejection and Spike Filtering
In the case where two or more edges appear in the data stream within a time period of
16 reference clocks, these are considered as interference and consequently no
additional clock adjustment is performed.
Phase Adjustment
In the case where an edge appears in the data stream within the PA fields of the time
window, the phase will be adjusted by 1/16 of the data clock.
Phase Shift (NRZ, NRZI only)
In the case where an edge appears in the data stream within the PS fields of the time
window, a second sampling of the bit is forced and the phase is shifted by 180 degrees.
Note: Edges in all other parts of the time window will be ignored.
This operation facilitates a fast and reliable synchronization for most common
applications. Above all, it implies a very fast synchronization because of the phase shift
feature: one edge on the received data stream is enough for the DPLL to synchronize,
thereby eliminating the need for synchronization patterns sometimes called preambles.
However, in case of extremely high jitter of the incoming data stream the reliability of the
clock recovery cannot be guaranteed.
The version 2 of ESCC2 offers the option to disable the Phase Shift function for NRZ and
NRZI encodings by setting bit CCR3:PSD. In this case, the PA fields are extended as
shown in figure 39b.
Semiconductor Group
88
07.96