SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 77

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

7.2
The receiver is generally activated by setting the RAC bit in the MODE register.
Additionally, the CD signal may be used to control data reception. After issuing the
HUNT command, the receiver monitors the incoming data stream for the presence of
specified SYN character(s). However, data reception is still disabled. If synchronization
is gained by detecting the SYN character(s), SCD interrupt is generated and all data is
pushed to RFIFO, i.e. control sequences, data characters and optional CRC frame
checking sequence (the LSB is received first). In normal operation, SYN characters are
excluded from storage to RFIFO. SYN character length can be specified independently
of the selected data character length. If required, the character parity bit and/or parity
status is FIFOed together with each data byte.
As an option, the loading of SYN characters in RFIFO may be enabled by setting the
SLOAD bit in register RFC. Note that in this case SYN characters are treated as data.
Consequently, for correct operation it must be guaranteed that SYN character length
equals the character length + optional parity bit. This is the user’s responsibility.
Filling of the accessible part of RFIFO is controlled by a programmable threshold level.
RFIFO read is requested by interrupt (RPF) or DMA.
Reception is stopped if
1. the receiver is deactivated by resetting the RAC bit, or
2. the CD signal goes inactive (if Carrier Detect Auto Start is enabled), or
3. the HUNT command is issued again, or
4. the Receiver Reset command (RRES) is issued, or
5. a programmed Termination Character has been found (optional).
On actions 1. and 2., reception remains disabled until the receiver is activated again.
After this is done, and generally in cases 3. and 4., the receiver returns to the
(non-synchronized) Hunt state. In case 5. a HUNT command has to be issued.
Reception of data is internally disabled until synchronization is regained.
Note: Further checking of frame length, extraction of text or data information and
Semiconductor Group
verifying the Frame Checking Sequence (e.g. CRC) has to be done by the
microprocessor.
Data Reception
Character Oriented Serial Mode (MONOSYNC/BISYNC)
77
SAB 82532/SAF 82532
07.96