SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 220

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

Semiconductor Group
Channel Configuration Register 2 (CCR2)
Access: read/write
Value after RESET: 00
The meaning of the individual bits in CCR2 depends on the clock mode selected via
CCR1 as follows:
clock mode 0b, 2, 3, 6,
Note: Unused bits have to be set to logical ‘0’.
SOC1, SOC2 …
BR9, BR8 …
XCS0, RCS0 …
clock mode 0a, 1
clock mode
clock mode
CCR2
7
4
5
SOC1
SOC1
SOC1
BR9
7
Special Output
In a bus configuration (selected via CCR0) defines the function of
pin RTS as follows:
0X … RTS output is activated during transmission.
10 … RTS output is always ‘high’ (RTS disabled).
11 … RTS indicates the reception of a data frame (active ‘low’).
In a point-to-point configuration (selected via CCR0) the TxD and
RxD pins may be flipped.
0X … data is transmitted on TxD, received on RxD (normal case).
1X … data is transmitted on RxD, received on TxD.
Baud Rate, Bit 9 … 8
High order bits, see description of BGR register.
Transmit/Receive Clock Shift, Bit 0
Together with XCS2, XCS1 (RCS2, RCS1) in TSAX (TSAR),
determines the clock shift relative to the frame synchronization
signal of the Transmit (Receive) time-slot.
A clock shift of 0 … 7 bits is programmable (clock mode 5 only).
H
SOC0
SOC0
SOC0
BR8
address: ch-A: 2E
XCS0
BDF
0
0
ch-B: 6E
220
RCS0
SSEL
0
0
H
H
TOE
TOE
TOE
Detailed Register Description
0
SAB 82532/SAF 82532
RWX
RWX
RWX
RWX
BISYNC Mode
0
0
0
0
DIV
DIV
DIV
DIV
07.96
0