SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 15
SAF82532N10V32A
Manufacturer Part Number
SAF82532N10V32A
Description
IC CONTROLLER 2-CH SER 68-PLCC
Manufacturer
Infineon Technologies
Datasheet
1.SAB82532H10V32A.pdf
(272 pages)
Specifications of SAF82532N10V32A
Controller Type
Serial Communications Controller (SCC)
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
8mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
SAF82532N10V32A
SAF82532N10V32AIN
SAF82532N10V32AIN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SAF82532N10V32A
Manufacturer:
Infineon Technologies
Quantity:
10 000
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1.3
P-LCC-68
25
Semiconductor Group
Pin Definitions and Functions (cont’d)
Pin No.
P-MQFP-80
57
Symbol
INTA
Input (I)
Output (O)
I
15
Function
Interrupt Acknowledge
If the interrupt is acknowledged via pin
INTA, an interrupt vector is output on
D0 … D7. All interrupt sources are
organized in 8 groups with fixed priority
(refer to chapter 2). The generated
interrupt vector refers to the interrupt
group with currently highest priority
(although more than one interrupt
source/group may be active). Reaction on
INTA signal depends on the bus interface
mode and the cascading mode in
conjunction with the Interrupt Enable pins
IE0 and IE1 (ref. to IPC register):
Motorola bus mode:
INT is reset with the rising edge of the
following valid INTA cycle if no further
interrupt is pending. The interrupt vector is
output with signal DS.
Siemens/Intel bus mode:
INT is reset with the rising edge of the
second valid INTA cycle (2-cycle ‘86
mode) if no further interrupt is pending.
Slave mode:
Interrupt acknowledge is accepted if an
interrupt signal has been generated and
the slave address provided via IE0, IE1
corresponds to the programmed value
(IPC register).
Daisy Chaining mode:
Interrupt acknowledge is accepted if an
interrupt signal has been generated and
Interrupt Enable input IE1 is active during
the following INTA cycle.
Note: Pins CS, DACKA and DACKB
have to be inactive during an INTA
cycle. If pin INTA is not used, it has
to be tied to
SAB 82532/SAF 82532
V
DD
.
Introduction
07.96
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