SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 91

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

8.3
Beside
point-to-multipoint (pt-mpt, or bus) configurations by means of internal idle and collision
detection/collision resolution methods.
In a pt-mpt configuration, comprising a central station (master) and several peripheral
stations (slaves), or in a multimaster configuration (see figure 16), data transmission
can be initiated by each station over a common transmit line (bus). In case more than
one station attempt to transmit data simultaneously (collision), the bus has to be
assigned to one station.
– In HDLC/SDLC mode, a collision-resolution procedure is implemented by the ESCC2.
– In BISYNC mode, the collision-resolution is implemented by the microprocessor.
– In ASYNC mode, a bus configuration is not recommended.
Prerequisites for bus operation are:
• NRZ encoding
• ‘OR’ing of data from every transmitter on the bus (this can be realized as a wired-OR,
• Feedback of bus information (CxD input).
The bus configuration is selected via the CCR0 register.
Note: Central clock supply for each station is not necessary if both the receive and
The bus mode can be operated independently of the clock mode, e.g. also during clock
mode 1 (receive and transmit strobe).
8.3.1
The idle state of the bus is identified by eight or more consecutive ‘1’s. When a device
starts transmission of a frame, the bus is recognized to be busy by the other devices at
the moment the first ‘zero’ is transmitted (e.g. first ‘zero’ of the opening flag in
HDLC mode).
After the frame has been transmitted, the bus becomes available again (idle).
Note: If the bus is occupied by other transmitters and/or there is no transmit request in
Semiconductor Group
Bus assignment is based on a priority mechanism with rotating priorities. This allows
each station a bus access within a predetermined maximum time delay (deterministic
CSMA/CD), no matter how many transmitters are connected to the serial bus.
using the TxD open drain capability)
transmit clock is recovered by the DPLL (clock modes 3a, 7a). This minimizes the
phase shift between the individual transmit clocks.
the ESCC2, logical ‘1’ will be continuously transmitted on TxD.
Bus Configuration
Bus Access Procedure
the
point-to-point
configuration,
91
the
Serial Interface (layer-1 functions)
ESCC2
SAB 82532/SAF 82532
effectively
supports
07.96