PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet
PSB3186FV14XT
Specifications of PSB3186FV14XT
Related parts for PSB3186FV14XT
PSB3186FV14XT Summary of contents
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ABM , ACE , AOP , ARCOFI ® ® FALC , GEMINAX , IDEC ® ® MUSAC , MuSLIC , OCTAT ® ® SCOUT , SICAT , SICOFI ® ® 10BaseV , 10BaseVX 10BaseS™, EasyPort™, VDSLite™ are ...
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Data Sheet Revision History: Previous Version: Page Subjects (major changes since last revision) Chapter 1 Comparison ISAC-S TE/ISAC-SX TE Chapter S- Transceiver Synchronization New 3.3.6.2 Chapter Test Functions extended 3.3.10 Chapter CDA Handler Description extended 3.7.1.1 Chapter TIC Bus Access ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 3.7 IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.1.11 SAP2 - SAPI2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.3.17 MOCR - MONITOR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 162 4.3.18 MSTA - MONITOR Status ...
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List of Figures Figure 1 Logic Symbol of the ISAC- ...
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List of Figures Figure 42 Example for Monitoring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 83 Maximum Line Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Figure 84 ...
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List of Tables Table 1 Comparison of the ISAC-SX TE with the previous version ISAC-S TE ...
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Overview The ISDN Subscriber Access Controller for Terminals ISAC-SX TE integrates a D-channel HDLC controller and a four wire S/T interface used to link voice/data terminals to the ISDN based on the ISAC-S TE PSB 2186, and ...
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Table 1 Comparison of the ISAC-SX TE with the previous version ISAC-S TE: Operating modes Supply voltage Technology Package Transceiver Transformer ratio for the transmitter receiver Test Functions Microcontroller Interface Command structure of the register access (SCI) Crystal Buffered 7.68 ...
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IOM-2 IOM-2 Interface Monitor channel programming C/I channels Layer 1 state machine Layer 1 state machine in software HDLC support D-channel FIFO size Reset Signals Reset Sources Interrupt Output Signals Pin SCLK Data Sheet ISAC-SX TE PSB 3186 Double clock ...
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ISDN Subscriber Access Controller for Terminals ISAC- 1.4 1.1 Features • Full duplex S/T interface transceiver according to ITU-T I.430 • Successor of ISAC-S TE PSB 2186 in 3.3 V technology • 8-bit parallel microcontroller ...
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One LED pin automatically indicating layer 1 activated state • Test loops • Sophisticated power management for restricted power mode • Power supply 3.3 V • 3.3 V output drivers, inputs are 5 V safe • Advanced CMOS technology ...
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Logic Symbol The logic symbol gives an overview of the ISAC-SX TE functions R/W ALE A0...7 AD0...4 AD5 / SCL Host Interface AD6 / SDR AD7 / SDX CS INT RES RSTO LED ...
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Typical Applications The ISAC- designed for the user area of the ISDN basic access, especially for subscriber terminal equipment with S interface. Figure 2 illustrates the general application fields of the ISAC-SX TE. S TE(1) TE(8) TE(1) ...
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Pin Configuration BCL DU DD FSC DCL VSS VSS VDD res_l EAW ACL res_c res_c res_c res_c res_c Figure 3 Pin Configuration of the ISAC-SX TE Data Sheet P-MQFP-64-1 P-TQFP-64 ...
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Table 2 ISAC-SX TE Pin Definitions and Functions Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD) Host Interface ...
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Table 2 ISAC-SX TE Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD) 15 AD6 I/O SDR I 16 AD7 I/O SDX R/W ...
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Table 2 ISAC-SX TE Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD) 41 ALE INT OD (O) 5 RES I 38 AMODE I IOM-2 Interface 52 ...
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Table 2 ISAC-SX TE Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD SDS O Miscellaneous 43 SX1 O 44 SX2 O 47 SR1 I 48 SR2 I ...
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Table 2 ISAC-SX TE Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD n. res. 57 res_l I 30, 31, res_c I 32, 60, 61, ...
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Description of Functional Blocks 3.1 General Functions and Device Architecture Figure 4 shows the architecture of the ISAC-SX TE containing the following functions: • S/T-interface transceiver supporting TE mode • Different host interface modes: - Parallel microcontroller interface (Siemens/Intel ...
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Figure 4 Functional Block Diagram of the ISAC-SX TE Data Sheet Peripheral Devices IOM-2 Interface IOM-2 Handler D-channel MON TIC C/I HDLC Handler RX/TX FIFOs Host Interface Reset Interrupt SCI -generation Host 26 ISAC-SX TE PSB 3186 Description ...
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Microcontroller Interfaces The ISAC-SX TE supports a serial or a parallel microcontroller interface. For applications where no controller is connected to the ISAC-SX TE microcontroller interface programming is done via the IOM-2 MONITOR channel from a master device. In ...
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Serial Control Interface (SCI) The serial control interface (SCI) is compatible to the SPI interface of Motorola or Siemens C510 family of microcontrollers. The SCI consists of 4 lines: SCL, SDX, SDR and CS. Data is transferred via the ...
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Programming Sequences The basic structure of a read/write access to the ISAC-SX TE registers via the serial control interface is shown in write sequence: header SDR 7 read sequence: header SDR 7 SDX Figure 6 Serial Control Interface Timing ...
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Header 40 : Non-interleaved A-D-A-D Sequences H The non-interleaved A-D-A-D sequence gives direct read/write access to the complete address range and can have any length. In this mode SDX and SDR can be connected together allowing data transmission on one ...
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Header 41 : Non-interleaved A-D-D-D Sequence H This sequence allows in front of the A-D-D-D write access a non-interleaved A-D-A-D read access. This mode is useful for reading status information before writing to the HDLC XFIFO. The termination condition of ...
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Note: If the multiplexed address/data bus type (3) is selected, the unused address pins A0-A7 must be tied read/write access to the ISAC-SX TE registers can be done in multiplexed or non- multiplexed mode: • In non-multiplexed ...
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Interrupt Structure Special events in the device are indicated by means of a single interrupt output, which requests the host to read status information from the device or transfer data from/to the device. Since only one interrupt request pin ...
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Reset Generation Figure 9 shows the organization of the reset generation of the device. . C/I Code Change 125µs £ t £ 250µs (Exchange Awake) EAW 125µs £ t £ 250µs (Subscriber Awake) 125µs £ t £ 250µs Watchdog ...
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C/I Code Change (Exchange Awake) A change in the downstream C/I channel (C/I0) generates an external reset pulse of 125 µs £ t £ 250 µs. • EAW (Subscriber Awake) A low level on the EAW input starts the ...
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Table 7 ISAC-SX TE Timers Address Register 24 TIMR1 H 65 TIMR2 H When the programmed period has expired an interrupt is generated and indicated in the auxiliary interrupt status ISTA.AUX. The source of the interrupt can be read from ...
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CNT VALUE TIMR1 Figure 11 Timer 1 Register Timer 2 The host starts and stops timer 2 in TIMR2.CNT is operating in count down mode, for TIMR2.TMD=1 a periodic interrupt AUXI.TIN2 is ...
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Activation Indication via Pin ACL The activated state of the S-interface is directly indicated via pin ACL (Activation LED). An LED with pre-resistance may directly be connected to this pin and a low level is driven on ACL as ...
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S/T-Interface The layer-1 functions for the S/T interface of the ISAC-SX TE are: – line transceiver functions for the S/T interface according to the electrical specifications of ITU-T I.430; – conversion of the frame structure between IOM-2 and S/T ...
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ISAC- The maximum line attenuation tolerated by the ISAC- kHz. TR ISAC-SX TE TE1 £ £ .... ISAC-SX TE TE1 Figure 15 Wiring Configurations in ...
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Figure 16 S/T -Interface Line Code Frame Structure Each S/T frame consists of 48 bits at a nominal bit rate of 192 kbit/s. For user data (B1+B2+D) the frame structure applies to a data rate of 144 kbit/s (see In ...
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F Framing Bit – L. D.C. Balancing Bit – D D-Channel Data Bit – E D-Channel Echo Bit – F Auxiliary Framing Bit A – N – B1 B1-Channel Data Bit – B2 B2-Channel Data Bit – A Activation ...
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Frame Number NT-to-TE F Bit Position A 1 ONE 2 ZERO 3 ZERO 4 ZERO 5 ZERO 6 ONE 7 ZERO 8 ZERO 9 ZERO 10 ZERO 11 ONE 12 ZERO 13 ZERO 14 ZERO 15 ZERO 16 ONE 17 ...
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Data Transfer and Delay between IOM-2 and S/T In the state F7 (Activated) the B1, B2, D and E bits are transferred transparently from the S/T to the IOM-2 interface. In all other states ’1’s are transmitted to the ...
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-> -> FSC Mapping of B-Channel Timeslots Mapping of a 4-bit group of D-bits on S and IOM depends ...
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VCM+0.525V '1' VCM '-0' VCM-0.525V Level '+0' VCM-0.525V '1' VCM '-0' VCM+0.525V Figure 20 Equivalent Internal Circuit of the Transmitter Stage 3.3.5 Receiver Characteristics The receiver consists of a differential input stage, a peak detector and a set of ...
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S/T Interface Circuitry For both, receive and transmit direction a 1:1 transformer is used to connect the ISAC transceiver to the 4 wire S/T interface. Typical transformer characteristics can be found in the chapter on electrical characteristics. ...
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Protection Circuit for Transmitter SX1 SX2 Figure 23 External Circuitry for Transmitter Figure 23 illustrates the secondary protection circuit recommended for the transmitter. The external resistors ( ... are required in order to adjust the ...
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Note capacitors are optional for noise reduction Figure 24 External Circuitry for Symmetrical Receivers Between each receive line and the transformer resistor is used. This value is split into two resistors: one ...
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S-Transceiver Synchronization Synchronization problems can occur on a S-Bus that is not terminated properly. Therefore recommended to change the resistor values in the receive path. The sum of both resistors is increased from (1.8 ...
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An activation initiated from the exchange side will have the consequence that a clock signal is provided automatically if TR_CONF0.LDD is set to ’0’. If TR_CONF0.LDD is set to ’1’ the microcontroller has to take care of an interrupt caused ...
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Test Functions The ISAC-SX TE provides test and diagnostic functions for the S/T interface: Note: For more details please refer to the application note “Test Function of new S- Transceiver family” – The internal local loop (internal Loop A) ...
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S/T interface according to the modified AMI code are initiated via a C/I command written in CIX0 register (see Two kinds of test signals may be transmitted by the ISAC-SX: – The ...
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Clock Generation Figure 28 shows the clock system of the ISAC-SX TE. The oscillator is used to generate a 7.68 MHz clock signal (f DCL (1536 kHz) and BCL (768 kHz) synchronous to the received S/T frames. The FSC ...
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Note input output; 1) The S transceiver can be disabled (TR_CONF0.DIS_TR=1) so the IOM clocks become inputs and with IOM_CR.CLKM the DCL input can be selected to double clock (0) or single bit clock (1). 2) ...
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Oscillator Clock Output C768 The ISAC-SX TE derives its system clocks from an external clock connected to XTAL1 (while XTAL2 is not connected) or from a 7.68 MHz crystal connected across XTAL1 and XTAL2. At pin C768 a buffered ...
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Control of Layer-1 The layer-1 activation / deactivation is controlled by an internal state machine via the IOM-2 C/I0 channel. The ISAC-SX TE layer-1 control flow is shown in Command CIX0 CI0 Data Register Indication CIR0 IOM-2 C/I0 channel ...
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IOM-2 Interface Interface INFO Figure 32 State Diagram Notation The following example illustrates the use of a state diagram with an extract of the TE state diagram. The state explained is “F3 deactivated”. The state may be ...
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State Machine TE Mode 3.5.1.1 State Transition Diagram (TE) Figure 33 shows the state transition diagram of the ISAC-SX TE state machine. Figure 34 shows this for the unconditional transitions (Reset, Loop, Test Mode i). Data Sheet Description of ...
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Pending Act. TIM RSY X TIM i4 F5 Unsynchronized i0*TO1 Synchronized Lost Framing ...
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SSP SCP SSP TMA SCP TIM DI Test Mode Figure 34 State Transition Diagram of Unconditional Transitions (TE) 3.5.1.2 States (TE) F3 Pending Deactivation State after deactivation from the S/T interface by info 0. Note that ...
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F7 Activated The receiver has synchronized and detects info 4. All user channels are now conveyed transparently to the IOM-2 interface. To transfer user channels transparently to the S/T interface either the command AR8 or AR10 has to be issued ...
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C/I Codes (TE) Command Activation Request with priority class 8 Activation Request with priority class 10 Activation Request Loop ARL Deactivation Indication Reset Timing Test mode SSP Test mode SCP Note: In the activated states (AI8, AI10 or AIL ...
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Indication Deactivation Request Reset Test Mode Acknowledge Slip Detected Resynchronization during level detect Deactivation Request from F6 Power up Activation request Activation request loop ARL Illegal Code Violation Activation indication loop Activation indication with priority class 8 Activation indication with ...
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Infos on S/T (TE) Receive Infos on S/T (Downstream) Name info 0 info 2 info 4 info X Transmit Infos on S/T (Upstream) Name info 0 info 1 info 3 Test info 1 Test info 2 Data Sheet Abbr. ...
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Command/ Indicate Channel Codes (C/I0) - Overview The table below presents all defined C/I0 codes. A command needs to be applied continuously until the desired action has been initiated. Indications are strictly state orientated. Refer to the state diagrams ...
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Control Procedures 3.6.1 Example of Activation/Deactivation An example of an activation/deactivation of the S/T interface initiated by the terminal with the time relationships mentioned in the previous chapters is shown RSY Figure 35 ...
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IOM-2 Interface The ISAC-SX TE supports the IOM-2 interface in terminal mode with single clock and double clock. The IOM-2 interface consists of four lines: FSC, DCL, DD and DU. Another clock signal BCL provides a single bit clock. ...
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IOM-2 Frame Structure (TE Mode) The frame structure on the IOM-2 data ports (DU,DD master device in IOM-2 terminal mode is shown in Figure 36 IOM Ò -2 Frame Structure in Terminal Mode The frame is composed of ...
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IOM-2 Handler The IOM-2 handler offers a great flexibility for handling the data transfer between the different functional units of the ISAC-SX TE and voice/data devices connected to the IOM-2 interface. Additionally it provides a microcontroller access to all ...
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SDS BCL DCL FSC DD DU Figure 37 Architecture of the IOM Handler (Example Configuration) Data Sheet Description of Functional Blocks Data C/I0 B2, B1, D, Data D Data C/I1 Data C/I0 Data Bus TIC Data Monitor Data CDA ...
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Controller Data Access (CDA) With its four controller data access registers (CDA10, CDA11, CDA20, CDA21) the ISAC-SX TE IOM-2 handler provides a very flexible solution for the host access IOM-2 timeslots. However, in the normal ...
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Data”. Besides that none of the IOM timeslots must be assigned more than one input and output of any functional unit. . TSa 1 0 Enable output input * (EN_O0) (EN_I0) CDAx0 1 0 TSa x ...
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Looping Data TSa CDA10 TSa .TSS: .DPS ’0’ .SWAP b) Shifting Data TSa CDA10 .TSS: TSa .DPS ’0’ .SWAP c) Switching Data TSa CDA10 .TSS: TSa .DPS ’0’ .SWAP Figure 39 Examples for Data Access via CDAxy Registers a) ...
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Figure 40 shows the timing of looping TSa from 0...11) via CDAxy register. TSa is read in the CDAxy register from DU and is written one frame later on DD 0...11 FSC ...
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Shifting TSa ® TSb within one frame (a,b: 0...11 and b ³ a+2) FSC DU TSa (DD) CDAxy b) Shifting TSa ® TSb in the next frame (a,b: 0...11 and ( <a) FSC DU TSa ...
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Monitoring Data Figure 42 gives an example for monitoring of two IOM-2 timeslots each simultaneously. For monitoring on DU and/or DD the channel registers with even numbers (CDA10, CDA20) are assigned to timeslots with even numbers ...
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Synchronous Transfer While looping, shifting and switching the data can be accessed by the controller between the synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). The microcontroller access to the CDAxy registers can be synchronized by means of ...
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Table 10 Examples for Synchronous Transfer Interrupts Enabled Interrupts (Register MSTI) STI STOV ...
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Figure 44 shows some examples based on the timeslot structure. Figure a) shows at which point in time an STI and STOV interrrupt is generated for a specific timeslot. Figure b) is identical to example 3 above, figure c) corresponds ...
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Restrictions Concerning Monitoring and Shifting Data Due to the hardware design, there are some restrictions for the CDA shifting data function and for the CDA monitoring data function. The selection of the CDA registers is restricted if other functional blocks ...
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Example: w CDA1_CR = 00 (inputs and outputs are disabled CDA10 = 5A (example CDA10 = FF (old value of previous programming CDA1_CR = 02 (output of CDA10 is enabled CDA10 = ...
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FSC DD, TS0 TS1 SDS (Example1) SDS (Example2) SDS (Example3) Example 1: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 Example 2: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 Example 3: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 For all examples SDS_CONF.SDS_BCL must be set to “0”. Figure ...
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Strobed IOM-2 Bit Clock The strobed IOM-2 bit clock is active during the programmed window. Outside the programmed window a ’0’ is driven. Two examples are shown in FSC DD, TS0 TS1 SDS (Example1) SDS (Example2) Setting ...
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The DPS bit in the same register selects between an output respectively and with EN_MON the MONITOR data can be enabled/disabled. The default value is MONITOR channel 0 (MON0) enabled and transmission on DD. IOM-2 MONITOR ...
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Handshake Procedure The MONITOR channel operates on an asynchronous basis. While data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure using the MONITOR Channel Receive (MR) and ...
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P µ MIE = 1 MOX = ADR MXC = 1 MAC = 1 MDA Int. MOX = DATA1 MDA Int. MOX = DATA2 MDA Int. MXC = 0 MAC = 0 Figure 48 MONITOR Channel Protocol (IOM-2) Before starting ...
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As a result, the first MONITOR byte is acknowledged by the receiving device setting the MR bit to ’0’. This causes a MONITOR Data Acknowledge MDA interrupt status at the transmitter. A new MONITOR data byte can now be written ...
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Since a double last-look criterion is implemented the receiver is able to receive the MON slot data at least twice (in two consecutive frames), the receiver waits for the acknowledge of the reception of two identical bytes in two ...
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IOM -2 Frame No. MX (DU) MR (DD) Figure 49 Monitor Channel, Transmission Abort requested by the Receiver IOM -2 Frame No. MR (DU) MX (DD) Figure 50 Monitor Channel, Transmission Abort requested by the Transmitter IOM -2 Frame No. ...
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MONITOR Channel Programming as a Master Device As a master device the ISAC-SX TE can program and control other devices attached to the IOM-2 interface. The master mode is selected by default if one of the possible microcontroller interfaces ...
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DU 1st byte value DU 2nd byte value e.g. 000001 ISAC-SX TE PSB 3186 V 1.4 This identification sequence is usually done once, when the terminal is connected for the first time. This function is used so that the software ...
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MONITOR Interrupt Logic Figure 52 shows the MONITOR interrupt structure of the ISAC-SX TE. The MONITOR Data Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt Enable (MRE) and MR bit Control (MRC). The MONITOR channel End ...
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A new code must be found in two consecutive IOM-2 frames to be considered valid and to trigger a C/I code change interrupt status (double last look criterion). In the transmit direction, the ...
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MASK ST CIC WOV TRAN MOS ICD Interrupt Figure 53 CIC Interrupt Structure 3.7.5 D-Channel Access Control D-channel access control is defined to guarantee all connected TEs and HDLC controllers a fair chance to transmit data in the D-channel. Collisions ...
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ICC (7) . TIC-Bus . on IOM-2 . ICC (2) ICC (1) D-channel control Figure 54 Applications of TIC Bus in IOM-2 Bus Configuration The arbitration mechanism is implemented in the last octet in IOM-2 channel 2 of the IOM-2 ...
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DU Figure 55 Structure of Last Octet of Ch2 on DU When the TIC bus is seized by the ISAC-SX TE, the bus is identified to other devices as occupied via the DU Ch2 Bus Accessed-bit state ’0’ until the ...
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MON0 Figure 56 Structure of Last Octet of Ch2 on DD The Stop/Go bit is available to other layer-2 devices connected to the IOM-2 interface to determine if they can access the S/T bus D channel. The ...
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D-channel control TE 1 D-channel control D-channel control TE 8 Figure 57 D-Channel Access Control on the S-Interface S-Bus D-channel Access Control in the ISAC-SX TE The above described priority mechanism is fully implemented in ...
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Activation/Deactivation of IOM-2 Interface The IOM-2 interface can be switched off in the inactive state, reducing power consumption to a minimum. In this deactivated state is FSC = ’1’, DCL and BCL = ’0’ and the data lines are ...
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After the clocks have been enabled this is indicated by the PU code in the C/I channel and, consequently CIC interrupt. The DU line may be released by resetting the Software Power Up bit IOM_CR =’0’ and the ...
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HDLC Controller The ISAC-SX TE contains an HDLC controller for the layer-2 functions of the D- channel protocol (LAPD). By setting the Enable HDLC channel bits (D_EN_x) in the DCI_CR register the HDLC controller can access the D or ...
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Operating Modes There are 5 different operating modes which can be selected via the mode selection bits MDS2-0 in the MODED registers: Non-Auto Mode (MDS2-0 = ’01x’) Characteristics: Full address recognition with one-byte (MDS = ’010’) or two-byte (MDS = ...
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Data Reception 3.8.2.1 Structure and Control of the Receive FIFO The cyclic receive FIFO buffer with a length of 64 byte has a variable FIFO block size (threshold bytes which can be selected ...
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The RFIFOD requests service from the microcontroller by setting a bit in the ISTAD register, which causes an interrupt (RPF, RME, RFO). The microcontroller then reads status information (RBCHD,RBCLD), data from the RFIFOD and then may change the receive FIFO ...
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RAM EXMD.RFBS=11 so after the first 4 bytes of a new frame have been stored in the fifo an receive pool full interrupt ISTAD.RPF is set. HDLC Receiver µP RAM HDLC Receiver RSTA The HDLC receiver has written further data ...
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Possible Error Conditions During Reception of Frames If parts of a frame get lost because the receive FIFO is full, the Receive Data Overflow (RDO) byte in the RSTAD byte will be set complete frame is lost, i.e. ...
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N In case of RME the last byte in RFIFO contains 1) * the receive status information RSTA Figure 61 Data Reception Procedures Figure 62 gives an example of an interrupt controlled reception sequence, supposed that a long frame (68 ...
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The host reads the first data block from RFIFOD and acknowledges the reception by RMC. Meanwhile the second data block is received and stored in RFIFOD. • The second 32 byte block is indicated by RPF which is read ...
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MDS2 MDS1 MDS0 MODE Non Auto/ Non Auto Transparent Transparent Transparent 2 Description of Symbols: Compared with registers Stored in FIFO/registers Figure 63 ...
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Table 16 Receive Information at RME Interrupt Information Type of frame (Command/ Response) Recognition of SAPI Recognition of TEI Result of CRC check (correct/incorrect) Valid Frame Abort condition detected (yes/no) Data overflow during reception of a frame (yes/no) Number of ...
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Data Transmission 3.8.3.1 Structure and Control of the Transmit FIFO The cyclic transmit FIFO buffer with a length of 64 byte has a variable FIFO block size (threshold bytes (programmable) which can be selected by ...
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XDOV (Transmit Data Overflow), indicating that the data block size has been exceeded, i.e. more than byte were entered and data was overwritten. – XFW (Transmit FIFO Write Enable), indicating that data can be written to ...
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XFIFOD, so any number of bytes smaller than the selected XFBS may be stored in the FIFO during one “write block“ access cycle. Similar to RFBS for the receive FIFO, a new setting of XFBS takes ...
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Command XTF Figure 64 Data Transmission Procedure The following description gives an example for the transmission byte frame with a selected block size of 32 byte: • The host writes 32 bytes to the XFIFOD, issues an ...
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Transmit Frame WR 32 Bytes 32 Bytes XPR XTF Figure 65 Transmission Sequence Example 3.8.3.2 Transmit Frame Structure The transmission of transparent frames (XTF command) is shown in For transparent frames, the whole frame including address and control field must ...
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Access to IOM-2 Channels By setting the enable HDLC data bits (D_EN_D, D_EN_B1, D_EN_B2) in the DCI_CR register the HDLC controller can access the D, B1 and B2 channels or any combination of them. In all modes (except extended ...
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HDLC Controller Interrupts The cause of an interrupt related to the HDLC controller is indicated in the ISTA register by the ICD bit. This bit points to the interrupt source of the D-channel HDLC controller in the ISTAD register. ...
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Test Functions The ISAC-SX TE provides test and diagnostic functions for the S-interface and the D- channel: • Digital loop via TLP (Test Loop, TMD register) command bit of layer 2 is internally connected with the RX path of ...
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Test of layer-2 functions while disabling all layer-1 functions and pins associated with them (including clocking) via bit TR_CONF0.DIS_TR. The HDLC controllers can still operate via IOM-2. DCL and FSC pins become input. • loop at the analog end ...
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Detailed Register Description The register mapping of the ISAC- shown in FFh 70h 60h 40h 30h 00h Figure 69 Register Mapping of the ISAC-SX TE The register address range from 00 and the C/I-channel handler. The register ...
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The register summaries of the ISAC-SX TE are shown in the following tables containing the abbreviation of the register name and the register bits, the register address, the reset values and the register type (Read/Write). A detailed register description follows ...
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CIR0 CODR0 CIX0 CODX0 CIR1 CIX1 Transceiver NAME TR_ DIS_ 0 CONF0 TR TR_ 0 RPLL_ CONF1 ADJ TR_ DIS_ PDS CONF2 TX TR_STA RINF SQRR1 MSYN MFEN SQXR1 0 MFEN SQRR2 SQR21SQR22SQR23SQR24SQR31SQR32SQR33SQR34 SQRR3 SQR41SQR42SQR43SQR44SQR51SQR52SQR53SQR54 ISTATR 0 ...
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Transceiver NAME ACFG2 0 0 IOM Handler (Timeslot , Data Port Selection, CDA Data and CDA Control Register) Name 7 6 CDA10 Controller Data Access Register (CH10) CDA11 Controller Data Access Register (CH11) CDA20 Controller Data Access ...
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CDA1_ CDA2_ IOM Handler (Control Registers, Synchronous Transfer Interrupt Control), MONITOR Handler Name 7 6 TR_CR EN_ EN_ D B2R (CI_CS=0) TRC_CR 0 0 (CI_CS=1) DCI_CR DPS_ EN_ CI1 CI1 (CI_CS=0) DCIC_CR 0 0 ...
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MSTI STOV STOV 21 20 SDS_ 0 0 CONF MCDA MCDA21 MOR MOX MOSR MDR MER MDA MOCR MRE MRC MSTA 0 0 MCONF 0 0 Interrupt, General Configuration Registers NAME ISTA 0 0 MASK 1 1 ...
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Interrupt, General Configuration Registers NAME Data Sheet Detailed Register Description reserved 127 ISAC-SX TE PSB 3186 0 ADDR R/WRES 2003-01-30 ...
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D-channel HDLC Control and C/I Registers 4.1.1 RFIFOD - Receive FIFO D-Channel 7 RFIFOD A read access to any address within the range 00h-1Fh gives access to the “current” FIFO location selected by an internal pointer which is automatically ...
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RME ... Receive Message End One complete frame of length less than or equal to the defined block size (EXMD1.RFBS) or the last part of a frame of length greater than the defined block size has been received. The contents ...
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If an XDU interrupt occurs the transmit FIFO is locked until the XDU interrupt is read by the host (interrupt cannot be read if masked in MASKD). 4.1.4 MASKD - Mask Register D-Channel Value after reset MASKD ...
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XACI ... Transmitter Active Indication The D-channel HDLC-transmitter is active when XACI = ’1’. This bit may be polled. The XACI-bit is active when an XTF-command is issued and the frame has not been completely transmitted 4.1.6 CMDRD - Command ...
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XRES ... Transmitter Reset The D-channel HDLC transmitter is reset and the XFIFOD is cleared of any data. This command can be used by the microcontroller to abort a frame currently in transmission. Note: After an XPR interrupt further data ...
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MDS2-0 Mode Number of Address Bytes Transparent > 1 mode Transparent > 1 mode 2 Note: SAP1, SAP2: two programmable address values for the first received address byte (in the case of an ...
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EXMD1- Extended Mode Register D-channel 1 Value after reset EXMD1 XFBS RFBS XFBS … Transmit FIFO Block Size 0 … Block size for the transmit FIFO data is 32 byte 1 … Block size for the ...
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ITF… Interframe Time Fill Selects the inter-frame time fill signal which is transmitted between HDLC-frames. 0 … idle (continuous ’1’) 1 … flags (sequence of patterns: ‘0111 1110’) Note: ITF must be set to ’0’ for power down mode. In ...
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SAPI1 ... SAPI1 value Value of the first programmable Service Access Point Identifier (SAPI) according to the ISDN LAPD protocol. MHA... Mask High Address 0 …The SAPI address of an incomming frame is compared with SAP1, SAP2, SAPG. 1 …The ...
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RBCHD - Receive Frame Byte Count High D-Channel Value after reset RBCHD ... Overflow A ’1’ in this bit position indicates a message longer than (2 RBC8-11 ... Receive Byte Count Four ...
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TEI2 - TEI2 Register Value after reset TEI2 TEI2 ... Terminal Endpoint Identifier In all message transfer modes except in transparent modes 0, 1 and extended transparent mode, TEI2 is used by the ISAC-SX TE for ...
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CRC ... CRC Check The CRC is correct (1) or incorrect (0). RAB ... Receive Message Aborted The receive message was aborted by the remote station (1), i.e. a sequence of seven 1’s was detected before a closing flag. SA1-0 ...
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C/R ... Command/Response The C/R bit contains the C/R bit of the received frame (Bit1 in the SAPI address) Note: The contents of RSTAD corresponds to the last received HDLC frame duplicated into RFIFOD for every frame (last ...
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CIC1 ... C/I Code 1 Change A change in the received Command/Indication code in IOM-channel 1 has been recognized. This bit is set when a new code is detected in one IOM-frame reset by a read of CIR0. ...
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BAC ... Bus Access Control Only valid if the TIC-bus feature is enabled (MODED.DIM2-0). If this bit is set, the ISAC-SX TE will try to access the TIC-bus to occupy the C/I-channel even if no D-channel frame has to be ...
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CI1E ... C/I-Channel 1 Interrupt Enable Interrupt generation ISTA.CIC of CIR0.CIC1 is enabled (1) or masked (0). Data Sheet Detailed Register Description 143 ISAC-SX TE PSB 3186 2003-01-30 ...
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Transceiver Registers 4.2.1 TR_CONF0 - Transceiver Configuration Register 0 Value after reset TR_ DIS_ 0 CONF0 TR DIS_TR ... Disable Transceiver Setting DIS_TR to “1” disables the transceiver. In order to reenable the transceiver again, a ...
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TR_CONF1 - Transceiver Configuration Register 1 Value after reset TR_ 0 RPLL_ CONF1 ADJ RPLL_ADJ ... Receive PLL Adjustment 0: DPLL tracking step is 0.5 XTAL period per S-frame 1: DPLL tracking step is 1 XTAL ...
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The phase deviation is 2 S-bits minus 9 oscillator periods plus analog delay plus delay of the external circuitry. For general information please refer to RLP ... Remote Line Loop 0: Remote Line Loop open 1: Remote Line Loop ...
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SQRR1 - S/Q-Channel Receive Register 1 Value after reset SQRR MSYN MFEN For general information please refer to MSYN ... Multi-frame Synchronization State 0: The S/T receiver has not synchronized to the received F 1: The ...
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SQRR2 - S/Q-Channel Receive Register 2 Value after reset SQRR2 SQR21 SQR22 SQR23 SQR24 SQR31 SQR32 SQR33 SQR34 SQR21-24, SQR31-34... Received S Bits Received S bits in frames and 17 (SQR21-24, subchannel 2), ...
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LD ... Level Detection Any receive signal has been detected on the line. This bit is set to “1” (i.e. an interrupt is generated if not masked) as long as any receiver signal is detected on the line. RIC ... ...
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ACL ... ACL Function Select 0: Pin ACL automatically indicates the S-bus activation status by a LOW level. 1: The output state of ACL is programmable by the host in bit LED. Note: An LED with preresistance my directly be ...
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IOM-2 and MONITOR Handler 4.3.1 CDAxy - Controller Data Access Register xy 7 CDAxy Data registers CDAxy which can be accessed from the controller. Register Register Address CDA10 40 CDA11 41 CDA20 42 CDA21 43 4.3.2 XXX_TSDPxy - Time ...
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The position of B-channel data from the S-interface is programmed in TR_TSDP_BC1 and TR_TSDP_BC2. DPS ... Data Port Selection 0: The data channel xy of the functional unit XXX is output on DD. The data channel xy of the functional ...
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EN_I1, EN_I0 ... Enable Input CDAx0, CDAx1 0: The input of the CDAx0, CDAx1 register is disabled 1: The input of the CDAx0, CDAx1 register is enabled EN_O1, EN_O0 ... Enable Output CDAx0, CDAx1 0: The output of the CDAx0, ...
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CS2-0 ... Channel Select for Transceiver D-channel This register is used to select one of eight IOM channels to which the transceiver D-channel data is related to. Note: It should be noted that writing TR_CR.CS2-0 will also write to TRC_CR.CS2-0 ...
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Note: The timeslot for the C/I1 handler cannot be programmed but is fixed to IOM channel 1. D_EN_D ... Enable D-timeslot for D-channel controller D_EN_B2 ... Enable B2-timeslot for D-channel controller D_EN_B1 ... Enable B1-timeslot for D-channel controller These bits ...
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MON_CR - Control Register Monitor Data Value after reset MON_CR DPS EN_ MON For general information please refer to DPS ... Data Port Selection 0: The Monitor data is output on DD and input from DU ...
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ENS_TSS ... Enable Serial Data Strobe of timeslot TSS ENS_TSS+1 ... Enable Serial Data Strobe of timeslot TSS+1 0: The serial data strobe signal SDSx is inactive during TSS, TSS+1 1: The serial data strobe signal SDSx is active during ...
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A write access to CS2-0 has effect on the configuration of D- and C/I-channel, whereas a read access delivers the D-channel configuration only write access to CS2-0 has effect on the configuration of the C/I-channel only, whereas ...
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STI - Synchronous Transfer Interrupt Value after reset STI STOV STOV 21 20 For all interrupts in the STI register the following logical states are applied: 0: Interrupt is not activated 1: Interrupt is activated The ...
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ACKxy ... Acknowledge Synchronous Transfer Interrupt After an STIxy interrupt the microcontroller has to acknowledge the interrupt by setting the corresponding ACKxy bit to “1”. 4.3.11 MSTI - Mask Synchronous Transfer Interrupt Value after reset MSTI STOV ...
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DIOM_SDS ... DU/DD on IOM Controlled via SDS 0: The pin SDS and its configuration settings are used for serial data strobe only. The IOM-2 data lines are not affected. 1: The DU/DD lines are deactivated during the during High/Low ...
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MOX - MONITOR Transmit Channel Value after reset MOX Contains the MONITOR data to be transmitted in IOM-2 MONITOR channel according to the MONITOR channel protocol.The MONITOR channel (0-7) can be selected by setting the monitor ...
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MRC ... MR Bit Control Determines the value of the MR bit always ’1’. In addition, the MDR interrupt is blocked, except for the first byte of a packet (if MRE = 1 internally ...
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MCONF - MONITOR Configuration Register Value after reset MCONF 0 0 TOUT... Time-Out 0: The monitor time-out function is disabled 1: The monitor time-out function is enabled Data Sheet 164 ISAC-SX TE PSB ...
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Interrupt and General Configuration 4.4.1 ISTA - Interrupt Status Register Value after reset ISTA 0 0 For all interrupts in the ISTA register following logical states are applied: 0: Interrupt is not acitvated 1: Interrupt is ...
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MASK - Mask Register Value after reset MASK 1 1 For the MASK register following logical states are applied: 0: Interrupt is enabled 1: Interrupt is disabled Each interrupt source in the ISTA register can selectively ...
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AUXM - Auxiliary Mask Register Value after reset AUXM 1 1 For the MASK register following logical states are applied: 0: Interrupt is enabled 1: Interrupt is disabled Each interrupt source in the AUXI register can ...
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The IOM interface clock and frame signals are always active, "Power Down" state included. The states "Power Down" and "Power Up" are thus functionally identical except for the indication 1111 and PU = 0111. With the C/I ...
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If RSS = ’10’ is selected the following two reset sources generate a reset pulse of 125 µs £ t £ 250µs at the RSTO pin: - External (Subscriber) Awake (EAW) The EAW input pin serves as a request ...
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DESIGN ... Design Number The design number allows to identify different hardware designs of the ISAC- software 1.4 H (all other codes reserved) 4.4.8 SRES - Software Reset Register Value after reset ...
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By writing ’0’ to CNT the timer is immediately stopped. A value different from that determines the time period after which an interrupt will be generated. If the timer is already started with a certain CNT value and is written ...
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Electrical Characteristics 5.1 Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature Input/output voltage on any pin with respect to ground Maximum voltage on any pin with respect to ground Note: Stresses above those listed here may cause ...
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DC Characteristics = 3.3 V ± 5 Parameter H-input level (except pin SR1/2) L-input level (except pin SR1/2) H-output level (except pin XTAL2, SX1/ 2) L-output level (except pin XTAL2, SX1/ 2) ...
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Capacitances = 25 ° 3 grounded. Parameter Input Capacitance I/O Capacitance Output Capacitance against V SS Data Sheet ± SSA SS Symbol Limit ...
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Oscillator Specification Recommended Oscillator Circuits Crystal Oscillator Mode Figure 70 Oscillator Circuits Parameter Frequency Frequency calibration tolerance Load capacitance Oscillator mode Note important to note that the load capacitance ...
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AC Characteristics = ° 3 Inputs are driven to 2.4 V for a logical "1" and to 0.45 V for a logical "0". Timing measurements are made at 2.0 V ...
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IOM-2 Interface Timing Data is transmitted with the rising edge of DCL and sampled with its falling edge. Below figure shows double clock mode timing (the length of a timeslot is 2 DCL cycles), however, the timing parameters are ...
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Note: Min. value in synchronous state, max. value in non-synchronous state. This results in a phase shift of FSC when the S-Bus gets activated, this is the FSC signal is shifted by 135 ns. DCL Clock Output Characteristics 2.3 V ...
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Microcontroller Interface Timing 5.7.1 Serial Control Interface (SCI) Timing SCL t 6 SDR SDX Figure 74 SCI Interface Parameter SCI Interface SCL cycle time SCL high time SCL low time CS setup time CS hold time ...
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Parallel Microcontroller Interface Timing Siemens/Intel Bus Mode The data read and write timing is the same for multiplexed and non multiplexed bus operation (Figure 75 and timing in multiplexed mode and Figure 75 Microprocessor Read Cycle Figure 76 Microprocessor ...
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A0-A7 Figure 78 Non-Multiplexed Address Timing Motorola Bus Mode The Motorola Bus is non multiplexed. The data timing is shown in Figure 80 (write). The corresponding address timing (for both read and write) ...
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D0-7 Figure 80 Microprocessor Write Cycle Data Sheet t DSD t RWD Data 182 ISAC-SX TE PSB 3186 Electrical Characteristics ITT09679 2003-01-30 ...
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AD0 - AD7 A0-7 Figure 81 Non-Multiplexed Address Timing Microprocessor Interface Timing Parameter ALE pulse width Address setup time to ALE Address hold time from ALE Address latch setup time to WR, RD Address setup time Address ...
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Reset Parameter Symbol Length of active t RES low state RES Figure 82 Reset Signal RES Data Sheet Limit Values Unit min DCL clock cycles t RES 184 ISAC-SX TE PSB 3186 Electrical Characteristics Test ...
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S-Transceiver Parameter = 3.3 V ± 5 Absolute value of output pulse amplitude | VSX2 – VSX1 | Transmitter output current Transmitter output impedance (SX1,2) Receiver Input impedance (SR1,2) Data Sheet Symbol ...
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Recommended Transformer Specification Parameter Symbol Transformer ratio Main inductance L Leakage inductance L Capacitance between C primary and secondary side Copper resistance R Note mode, at the pulse shape measurement with a load of 400 W (e.g. ...
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Line Overload Protection The maximum input current for the S-transceiver lines (under overvoltage conditions) is given as a function of the width of a rectangular input current pulse. The desctruction limits are shown in Figure i [ ...
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EMC / ESD Aspects To improve performance with respect to EMC and ESD requirements it is recommended to provide additional capacitors in the middle tap of the transformers (see below). The values for C1 and C2 should be in ...
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Package Outlines P-MQFP-64-1 (Plastic Metric Quad Flat Package) You can find all of the current packages, types of packing, and others on the Infineon Internet Page “Products”: http://www.infineon.com/products. SMD = Surface Mounted Device Data Sheet 189 ISAC-SX TE PSB ...
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P-TQFP-64-1 (Plastic Thin Quad Flat Package) You can find all of the current packages, types of packing, and others on the Infineon Internet Page “Products”: http://www.infineon.com/products. SMD = Surface Mounted Device Data Sheet 190 ISAC-SX TE PSB 3186 Package Outlines ...
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Appendix D-channel HDLC, C/I-channel Handler Name RFIFOD XFIFOD ISTAD RME RPF MASKD RME RPF STARD XDOV XFW CMDRD RMC RRES MODED MDS2 MDS1 MDS0 EXMD1 XFBS RFBS TIMR1 CNT SAP1 SAP2 RBCLD RBC7 RBCHD 0 0 ...
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CIR1 CIX1 Transceiver NAME TR_ DIS_ 0 CONF0 TR TR_ 0 RPLL_ CONF1 ADJ TR_ DIS_ PDS CONF2 TX TR_STA RINF SQRR1 MSYN MFEN SQXR1 0 MFEN SQRR2 SQR21SQR22SQR23SQR24SQR31SQR32SQR33SQR34 SQRR3 SQR41SQR42SQR43SQR44SQR51SQR52SQR53SQR54 ISTATR 0 x MASKTR 1 1 ...
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IOM Handler (Timeslot , Data Port Selection, CDA Data and CDA Control Register) Name 7 6 CDA10 Controller Data Access Register (CH10) CDA11 Controller Data Access Register (CH11) CDA20 Controller Data Access Register (CH20) CDA21 Controller Data Access Register (CH21) ...
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IOM Handler (Control Registers, Synchronous Transfer Interrupt Control), MONITOR Handler Name 7 6 TR_CR EN_ EN_ D B2R (CI_CS=0) TRC_CR 0 0 (CI_CS=1) DCI_CR DPS_ EN_ CI1 CI1 (CI_CS=0) DCIC_CR 0 0 (CI_CS=1) MON_CR DPS EN_ MON SDS_CR ENS_ ENS_ ...
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MOR MOX MOSR MDR MER MDA MOCR MRE MRC MSTA 0 0 MCONF 0 0 Interrupt, General Configuration Registers NAME ISTA 0 0 MASK 1 1 AUXI 0 0 AUXM 1 1 MODE1 0 0 MODE2 0 ...
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Index A Absolute maximum ratings 172 AC characteristics 176 ACFG2 register 149 ACKxy bits 159 ACL bit 149 Activation 67 Activation indication - pin ACL 38 Activation LED 38 Activation/deactivation of IOM-2 interface 100 Appendix 191 Applications 18 Architecture 25 ...
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Index EN_CI1 bit 154 EN_D bit 153 EN_I0 bit 152 EN_I1 bit 152 EN_ICV bit 144 EN_MON bit 156 EN_O0 bit 152 EN_O1 bit 152 EN_SFSC bit 145 EN_TBM bit 152 ENS_TSSx bits 156 Exchange awake 35 EXLP bit 144 ...
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Index MON_CR register 156 Monitor channel Error treatment 89 Handshake procedure 86 Interrupt logic 93 Master device 91 Slave device 91 Time-out procedure 92 Monitoring data 77 MOR register 161 MOS bit 165 MOSR register 162 MOX register 162 MRC ...
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Index Shifting data 73 SLIP bit 146 Software reset 35 SPU bit 157 SQC bit 148 SQR1-4 bits 147 SQR21-24 bits 148 SQR31-34 bits 148 SQR41-44 bits 148 SQR51-54 bits 148 SQRR1 register 147 SQRR2 register 148 SQRR3 register 148 ...
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