PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 112

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.8.3
3.8.3.1
The cyclic transmit FIFO buffer with a length of 64 byte has a variable FIFO block size
(threshold) of 16 or 32 bytes (programmable) which can be selected by setting the
corresponding XFBS bits in the EXMD register. There are three different interrupt
indications in the ISTAD register concerned with the transmission of data:
– XPR (Transmit Pool Ready) interrupt, indicating that a data block of up to 16 or 32 byte
– XDU (Transmit Data Underrun) interrupt, indicating that the transmission of the
– XMR (Transmit Message Repeat) interrupt, indicating that the transmission of the
Three different control commands are used for transmission of data:
– XTF (Transmit Transparent Frame) command, telling the ISAC-SX TE that up to 16 or
– XME (Transmit Message End) command, telling the ISAC-SX TE that the last data
– XRES (Transmitter Reset) command, resetting the HDLC transmitter and clearing the
Optionally two additional status conditions can be read by the host:
Data Sheet
can be written to the XFIFOD (fixed block size).
An XPR interrupt is generated either
• after an XRES (Transmitter Reset) command (which is issued for example for frame
abort) or
• when a data block from the XFIFOD is transmitted and the corresponding FIFO
space is released to accept further data from the host.
current frame has been aborted (seven consecutive ’1’s are transmitted) as the
XFIFOD holds no further transmit data. This occurs if the host fails to respond to an
XPR interrupt quickly enough.
complete last frame has to be repeated as a collision on the S bus has been detected
and the XFIFOx does not hold the first data bytes of the frame (collision after the 16th/
32nd byte or after the 32nd byte of the frame, respectively).
The occurence of an XDU or XMR interrupt clears the XFIFOD and an XMR interrupt
is issued together with an XDU or XMR interrupt, respectively. Data cannot be written
to the XFIFOD as long as an XDU/XMR interrupt is pending.
32 byte have been written to the XFIFOD and should be transmitted. A start flag is
generated automatically.
block written to the XFIFOD completes the corresponding frame and should be
transmitted. This implies that according to the selected mode a frame end (CRC +
closing flag) is generated and appended to the frame.
transmit FIFO of any data. After an XRES command the transmitter always sends an
abort sequence, i.e. this command can be used to abort a transmission. Pending
interrupt indications of the transmitter are not cleared by XRES, but have to be cleared
by reading these interutps.
Data Transmission
Structure and Control of the Transmit FIFO
112
Description of Functional Blocks
ISAC-SX TE
PSB 3186
2003-01-30