PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 82

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Example:
w CDA1_CR = 00
w CDA10 = 5A
r CDA10 = FF
w CDA1_CR = 02
r CDA10 = 5A
3.7.2
For timeslot oriented standard devices connected to the IOM-2 interface the ISAC-SX
TE provides an independent data strobe signal SDS. Instead of a data strobe signal a
strobed IOM-2 bit clock can be provided on pin SDS.
3.7.2.1
The strobe signal can be generated with every 8-kHz frame and is controlled by the
register SDS_CR. By programming the TSS bits and three enable bits (ENS_TSS,
ENS_TSS+1, ENS_TSS+3) a data strobe can be generated for the IOM-2 timeslots TS,
TS+1 and TS+3 and any combination of them.
The data strobe for TS and TS+1 are always 8 bits long (bit7 to bit0) whereas the data
strobe for TS+3 is always 2 bits long (bit7, bit6).
Figure 45
SDS is active during channel B2 on IOM-2 whereas in the second example during IC2
and MON1. The third example shows a strobe signal for 2B+D channels which can be
used e.g. for an IDSL (144kbit/s) transmission.
Data Sheet
shows three examples for the generation of a strobe signal. In example 1 the
Serial Data Strobe Signal and Strobed Data Clock
Serial Data Strobe Signal
H
H
H
(old value of previous programming)
(the programmed value can be read back)
(example)
H
H
(inputs and outputs are disabled)
(output of CDA10 is enabled)
82
Description of Functional Blocks
ISAC-SX TE
PSB 3186
2003-01-30