PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 34

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.2.4
Figure 9
.
Figure 9
Reset Source Selection
The internal reset sources C/I code change, EAW and Watchdog can be output at the
low active reset pin RSTO. The selection of these reset sources can be done with the
RSS2,1 bits in the MODE1 register according
The setting RSS2,1 = ’01’ is reserved for further use. In this case no reset except
software reset (SRES.RSTO) is output on RSTO. The internal reset sources set the
MODE1 register to its reset value.
Table 6
RSS2 Bit 1
0
0
1
1
Data Sheet
C/I Code Change
(Exchange Awake)
EAW
(Subscriber Awake)
Watchdog
Software Reset
Register (SRES)
Reset
Functional
Block
shows the organization of the reset generation of the device.
Internal Reset of all Registers
Reset Generation
Reset MODE1 Register
Reset Source Selection
D, C/I-channel (00
Transceiver (30
IOM-2 (40
MON-channel (5C
General Config (60
Reset Generation
RSS1 Bit 0
0
1
0
1
125µs £ t £ 250µs
125µs £ t £ 250µs
125µs £ t £ 250µs
125µs £ t £ 250µs
H
-5B
H
)
H
-3F
H
H
H
-2F
-5F
H
-6F
)
H
H
H
)
)
)
³ 1
'0'
'1'
C/I Code
Change
--
x
--
RSS1
'1x'
'00'
RSS2,1
34
Table
³ 1
Description of Functional Blocks
6.
EAW
--
x
--
' 01 '
reserved
(reserved)
'01'
RSS2,1
³ 1
Watchdog
Timer
--
--
x
ISAC-SX TE
Pin
RES
Pin
RSTO
PSB 3186
3186_21
2003-01-30