PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 96

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Figure 54
The arbitration mechanism is implemented in the last octet in IOM-2 channel 2 of the
IOM-2 interface
by software (µP access to the C/I channel) or by the ISAC-SX TE itself (transmission of
an HDLC frame in the D-channel). A software access request to the bus is effected by
setting the BAC bit (CIX0 register) to ’1’.
In the case of an access request, the ISAC-SX TE checks the Bus Accessed-bit BAC (bit
5 of last octet of CH2 on DU,
a logical ’1’. If the bus is free, the ISAC-SX TE transmits its individual TIC bus address
TAD programmed in the CIX0 register (CIX0.TBA2-0). The ISAC-SX TE sends its TIC
bus address TAD and compares it bit by bit with the value on DU. If a sent bit set to ’1’
is read back as ’0’ because of the access of another D-channel source with a lower TAD,
the ISAC-SX TE withdraws immediately from the TIC bus, i.e. the remaining TAD bits
are not transmitted. The TIC bus is occupied by the device which sends its address error-
free. If more than one device attempt to seize the bus simultaneously, the one with the
lowest address values wins. This one will set BAC=0 on TIC bus and starts D-channel
transmission in the same frame.
Data Sheet
D-channel
control
ICC (7)
ICC (2)
ICC (1)
.
.
.
Applications of TIC Bus in IOM-2 Bus Configuration
(Figure
TIC-Bus
on IOM-2
55). An access request to the TIC bus may either be generated
transceiver
Figure
S-
55) for the status "bus free“, which is indicated by
96
S-Interface
Description of Functional Blocks
NT
3086_09
U-Interface
ISAC-SX TE
PSB 3186
2003-01-30