PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 36

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Table 7
Address
When the programmed period has expired an interrupt is generated and indicated in the
auxiliary interrupt status ISTA.AUX. The source of the interrupt can be read from AUXI
(TIN1, TIN2) and each of the interrupt sources can be masked in AUXM.
Figure 10
Timer 1
The host controls the timer 1 by setting bit CMDRD.STI to start the timer and by writing
register TIMR1 to stop the timer. After time period T1 an interrupt (AUXI.TIN1) is
generated continuously if CNT= 7 or a single interrupt is generated after timer period T
if CNT<7
Data Sheet
24
65
H
H
(Figure
ISAC-SX TE Timers
Timer Interrupt Status Registers
11).
TRAN
MASK
AUX
MOS
CIC
ICD
Interrupt
ST
Register
TIMR1
TIMR2
TRAN
ISTA
AUX
MOS
CIC
ICD
ST
36
Modes
Periodic
Count Down
Periodic
Count Down
AUXM
TIN2
TIN1
EAW
WOV
Description of Functional Blocks
AUXI
TIN2
EAW
WOV
TIN1
Period
64 ... 2048 ms
64 ms ... 14.336 s
1 ... 63 ms
1 ... 63 ms
ISAC-SX TE
PSB 3186
2003-01-30