PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 152

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

CDAx_
CR
The position of B-channel data from the S-interface is programmed in TR_TSDP_BC1
and TR_TSDP_BC2.
DPS ... Data Port Selection
0: The data channel xy of the functional unit XXX is output on DD.
1: The data channel xy of the functional unit XXX is output on DU.
Note: For the CDA (controller data access) data the input is determined by the
TSS ... Timeslot Selection
Selects one of 32 timeslots (0...31) on the IOM-2 interface for the data channels.
4.3.3
Register
CDA1_CR
CDA2_CR
For general information please refer to
EN_TBM ... Enable TIC Bus Monitoring
0: The TIC bus monitoring is disabled
1: The TIC bus monitoring with the CDAx0 register is enabled. The TSDPx0 register
Data Sheet
The data channel xy of the functional unit XXX is input from DU.
The data channel xy of the functional unit XXX is input from DD.
must be set to 08
respectively (this selection is only valid if IOM_CR.TIC_DIS = 0).
CDA_CRx.SWAP bit. If SWAP = ’0’ the input for the CDAxy data is vice versa to
the output setting for CDAxy. If the SWAP = ’1’ the input from CDAx0 is vice versa
to the output setting of CDAx1 and the input from CDAx1 is vice versa to the output
setting of CDAx0. See controller data access description in
7
CDAx_CR - Control Register Controller Data Access CH1x
0
H
0
for monitoring from DU or 88
TBM
EN_
Register Address
4E
4F
H
H
EN_I1 EN_I0 EN_O1 EN_O0 SWAP
Chapter
152
3.7.1.1.
H
for monitoring from DD,
Detailed Register Description
Value after Reset
00
00
H
H
0
Chapter 3.7.1.1
ISAC-SX TE
PSB 3186
2003-01-30
RD/WR
(4E-4F)