PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 165

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

ISTA
4.4
4.4.1
Value after reset: 00
For all interrupts in the ISTA register following logical states are applied:
0: Interrupt is not acitvated
1: Interrupt is acitvated
ICD ... HDLC Interrupt from D-channel
An interrupt originated from the HDLC controller of the D-channel has been recognized.
ST ... Synchronous Transfer
This interrupt is generated to enable the microcontroller to lock on to the IOM timing for
synchronous transfers. The source can be read from the STI register.
CIC ... C/I Channel Change
A change in C/I channel 0 or C/I channel 1 has been recognized. The actual value can
be read from CIR0 or CIR1.
AUX ... Auxiliary Interrupts
Signals an interrupt generated from external awake (pin EAW), watchdog timer overflow,
timer1 or timer2. The source can be read from the auxiliary interrupt register AUXI.
TRAN ... Transceiver Interrupt
An interrupt originated in the transceiver interrupt status register (ISTATR) has been
recognized.
MOS ... MONITOR Status
A change in the MONITOR Status Register (MOSR) has occured.
Note: A read of the ISTA register clears none of the interrupts. They are only cleared by
Data Sheet
reading the corresponding status register.
7
Interrupt and General Configuration
ISTA - Interrupt Status Register
0
H
0
ST
CIC
165
AUX
TRAN MOS
Detailed Register Description
0
ICD
ISAC-SX TE
PSB 3186
2003-01-30
RD (60)