PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 10

• Manufacturer Part Number: PEF82912FV14XP
• Manufacturer: Lantiq

Specifications of PEF82912FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

List of Figures
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Data Sheet
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Application Example Q-SMINT
Control via µP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Control via IOM‚-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Serial Command Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Direct/Indirect Register Address Mode . . . . . . . . . . . . . . . . . . . . . . . . 24
Reset Generation of the Q-SMINT
IOM -2 Frame Structure of the Q-SMINT‚I . . . . . . . . . . . . . . . . . . . . . 28
Architecture of the IOM -2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Data Access via CDAx0 and CDAx1 register pairs . . . . . . . . . . . . . . . 32
Examples for Data Access via CDAxy Registers . . . . . . . . . . . . . . . . . 33
Data Access when Looping TSa from DU to DD . . . . . . . . . . . . . . . . . 34
Data Access when Shifting TSa to TSb on DU (DD) . . . . . . . . . . . . . . 35
Example for Monitoring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Interrupt Structure of the Synchronous Data Transfer . . . . . . . . . . . . . 39
Examples for the Synchronous Transfer Interrupt Control with
one STIxy enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Data Strobe Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
MONITOR Channel Protocol (IOM®-2) . . . . . . . . . . . . . . . . . . . . . . . . 44
Monitor Channel, Transmission Abort requested by the Receiver. . . . 47
Monitor Channel, Transmission Abort requested by the Transmitter. . 47
Monitor Channel, Normal End of Transmission . . . . . . . . . . . . . . . . . . 47
MONITOR Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CIC Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
D-Channel Arbitration: C with HDLC and Direct Access to TIC Bus . 52
D-Channel Arbitration: C with HDLC and no Access to TIC Bus . . . . 53
Structure of Last Octet of Ch2 on DU . . . . . . . . . . . . . . . . . . . . . . . . . 54
Structure of Last Octet of Ch2 on DD . . . . . . . . . . . . . . . . . . . . . . . . . 55
State Machine of the D-Channel Arbiter (Simplified View). . . . . . . . . . 57
Deactivation of the IOM
U-Superframe Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
U-Basic Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
U2B1Q Framer - Data Flow Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . 63
U2B1Q Deframer - Data Flow Scheme . . . . . . . . . . . . . . . . . . . . . . . . 63
Write Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Read Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
EOC Message Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
EOC Command/Message Transmission . . . . . . . . . . . . . . . . . . . . . . . 70
Maintenance Channel Filtering Options . . . . . . . . . . . . . . . . . . . . . . . . 76
M4 Bit Report Timing (Statemachine vs. µC). . . . . . . . . . . . . . . . . . . . 76
®
-2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
®
I: High Feature Intelligent NT . . . . . . 14
®
I . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PEF 82912/82913
2001-03-30
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