PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 67

• Manufacturer Part Number: PEF82912FV14XP
• Manufacturer: Lantiq

Specifications of PEF82912FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

•
Figure 27
2.3.5.2
The TIC bus is implemented to organize the access to the C/I0-channel and to the D-
channel from up to 7 D-channels HDLC controllers. The arbitration mechanism must be
activated by setting MODEH.DIM2-0=00x.
The arbitration mechanism is implemented in the last octet in IOM -2 channel 2 of the
IOM -2 interface (see
generated by software (µC access to the C/I0-channel via CIX0 register) or by an
external D-channel HDLC controller (transmission of an HDLC frame in the D-channel).
A software access request to the bus is effected by setting the BAC bit in register CIX0
to ’1’ (resulting in BAC = ’0’ on IOM -2).
In the case of an access request by the Q-SMINT I, the Bus Accessed-bit BAC (bit 5 of
last octet of CH2 on DU, see
indicated by a logical ’1’. If the bus is free, the Q-SMINT I transmits its individual TIC bus
address TAD programmed in the CIX0 register (CIX0.TBA2-0). While being transmitted
the TIC bus address TAD is compared bit by bit with the value read back on DU. If a sent
bit set to ’1’ is read back as ’0’ because of the access of an external device with a lower
TAD, the Q-SMINT I withdraws immediately from the TIC bus, i.e. the remaining TAD
bits are not transmitted. The TIC bus is occupied by the device which sends and reads
back its address error-free. If more than one device attempt to seize the bus
simultaneously, the one with the lowest address values wins. This one will set BAC=0 on
TIC bus and starts D-channel transmission in the same frame.
Data Sheet
D
E-Bit
TIC Bus Handling
D-Channel Arbitration: C with HDLC and no Access to TIC Bus
Q-SMINT I
S
Figure
Arbitr.
IOM-2 i/f
Prio
IOM-2
Figure
28). An access request to the TIC bus may either be
BAC
S/G
28) is checked for the status "bus free“, which is
S/G
HDLC
MC68302
µP - i/f
HDLC
CIR0
HDLC
CIX0
HDLC
e.g.
BAC
µC
53
U
•
and S/G-bit via TIC-Bus Handler
•
then transmit D-channel
µC has access to BAC, TBA-Bit
µC
C/I Channel
must poll S/G bit until S/G=0,
Handler
Functional Description
PEF 82912/82913
D
2001-03-30
.