PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 206

• Manufacturer Part Number: PEF82912FV14XP
• Manufacturer: Lantiq

Specifications of PEF82912FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

CI
FEBE/
NEBE
M56
M4
EOC
6 ms
12 ms
4.11.18
The Interrupt Mask register U-Interface selectively masks each interrupt source in the
ISTAU register by setting the corresponding bit to ‘1’.
Data Sheet
MASKU - Mask Register U-Interface
C/I code indication
the CI interrupt is generated independently on OPMODE.UCI
0 =
1 =
Far End/Near End Block Error indication
register M56R notifies whether a FEBE or NEBE has been detected
0 =
1 =
Validated new M56 bit data received from U-interface
0 =
1 =
Validated new M4 bit data received from U-interface
0 =
1 =
Validated new EOC data received from U-interface
0 =
1 =
6 ms timer for the transmission of EOC commands on U
0 =
1 =
Superframe marker (each 12 ms) is going to be issued on U in transmit
direction
Bellcore test requirement: SR-NWT-002397
0 =
1 =
inactive
CI code change has occurred
inactive
FEBE/NEBE occurred
inactive
change of any M5, M6 bit has been detected in receive direction
inactive
change of any M4 bit has been detected in receive direction
inactive
new EOC message has been received and acknowledged from U
inactive
indicates when a EOC command is going to be issued on U
inactive
indicates when a SF marker is going to be transmitted on U
192
Register Description
PEF 82912/82913
2001-03-30