PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 194

• Manufacturer Part Number: PEF82912FV14XP
• Manufacturer: Lantiq

Specifications of PEF82912FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

UCI
FEBE
MLT
CI_SEL
4.11.2
The M Bit Filter register defines the validation algorithm received Maintenance channel
bits (EOC, M4, M56) of the U-interface have to undergo before they are approved and
passed on to the µC.
MFILT
Reset Value:
Data Sheet
MFILT - M Bit Filter Options
Enable/Disable C Control of C/I Codes
0 =
1 =
Enable/Disable External Write Access to FEBE Bit in Register M56W
0 =
1 =
Enable/Disable Metallic Loop Termination Function
MLT status is reflected in bit MS2 and MS1 in register M56R
0 =
1 =
C/I Code Output Selection
by CI_SEL the user can switch:
– between the standard C/I indications of the NT state machine as
– newly defined C/I code indications which facilitates control and debugging
0 =
1 =
implemented in today’s IEC-Q versions or
14
external access to FEBE bit disabled - FEBE bit is controlled by
external access to FEBE bit enabled - FEBE bit is controlled by
MLT disabled
MLT enabled
Read access to register UCIR by the P is still possible
registers
In this case, the according C/I-channel on IOM
internal FEBE counter
external microprocessor
Standard NT state machine
compliant to NT state machine of today’s IEC-Q V4.3-V5.3
Simplified NT state machine
output of newly defined C/I code indications for enhanced
activation/deactivation control and debugging facilities
H
C control disabled - C/I codes are exchanged via IOM
C control enabled - C/I codes are exchanged via UCIR and UCIW
read*
180
)
/write
Register Description
®
PEF 82912/82913
-2 is idle ‘1111‘
Address:
®
-2
2001-03-30
61
H