PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 115

• Manufacturer Part Number: PEF82912FV14XP
• Manufacturer: Lantiq

Specifications of PEF82912FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

PEF 82912/82913
Functional Description
2.4.12
U-Transceiver Interrupt Structure
The U-Interrupt Status register (ISTAU) contains the interrupt sources of the U-
Transceiver
(Figure
50). Each source can be masked by setting the corresponding bit
of the U-Interrupt Mask register (MASKU) to ’1’. Such masked interrupt status bits are
not indicated when ISTAU is read and do not generate an interrupt request.
The ISTAU register is cleared on read access. The interrupt sources of the ISTAU
register (UCIR, EOCR, M4R, M56R) need not be evaluated.
When at time t1 an interrupt source generates an interrupt, all further interrupts are
collected. Reading the ISTAU register clears all interrupts set before t1, even if masked.
All interrupts, which are flagged after t1 remain active. After the ISTAU read access, the
next unmasked interrupt will generate the next interrupt at time t2. After t2 it is possible
to reprogram the MASKU register, so that all interrupts, which arrived between t1 and t2
are accessible.
Data Sheet
101
2001-03-30