PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 51

• Manufacturer Part Number: PEF82912FV14XP
• Manufacturer: Lantiq

Specifications of PEF82912FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Monitoring TIC Bus
Monitoring the TIC bus (TS11) is handled as a special case. The TIC bus can be
monitored with the registers CDAx0 by setting the EN_TBM (Enable TIC Bus Monitoring)
bit in the control registers CRx. The TSDPx0 must be set to 08
or 88
the odd numbered D-channel (TS3) simultaneously on DU and DD.
Synchronous Transfer
While looping, shifting and switching the data can be accessed by the controller between
the synchronous transfer interrupt (STI) and the synchronous transfer overflow interrupt
(STOV).
The microcontroller access to each of the CDAxy registers can be synchronized by
means of four programmable synchronous transfer interrupts (STIxy)
transfer overflow interrupts (STOVxy)
Depending on the DPS bit in the corresponding TSDPxy register the STIxy is generated
two (for DPS=’0’) or one (for DPS=’1’) BCL clock after the selected time slot
(CDA_TSDPxy.TSS). One BCL clock is equivalent to two DCL clocks.
In the following description the index xy
interrupt pairs (STI/STOV) out of the four CDA interrupt pairs (STI10/STOV10, STI11/
STOV11, STI20/STOV20, STI21/STOV21).
A STOVxy
acknowledged. However, if STIxy
STIxy1 which is enabled and not acknowledged.
Table 9
generated because a STI interrupt was not acknowledged before.
In example 1 only the STIxy
enabled, no interrupt will be generated even if STOV is enabled (example 2).
In example 3 STIxy
disabled. STIxy
generated due to STIxy
enabled, so STOVxy
In example 5 additionally the STIxy
generated due to STIxy
Compared to the previous example STOVxy
not generated and STOVxy
1)
2)
Data Sheet
In order to enable the STI interrupts the input of the corresponding CDA register has to be enabled. This is also
valid if only a synchronous write access is wanted. The enabling of the output alone does not effect an STI
interrupt.
In order to enable the STOV interrupts the output of the corresponding CDA register has to be enabled. This
is also valid if only a synchronous read access is wanted. The enabling of the input alone does not effect an
interrupt.
h
for monitoring from DD. By this it is possible to monitor the TIC bus (TS11) and
gives some examples for that. It is assumed that a STOV interrupt is only
0
is related to its STIxy
1
is disabled but its STOVxy
0
0
and STOVxy
is enabled and generated and the corresponding STOVxy
0
0
and STOVxy
. In example 4 additionally the corresponding STOVxy
1
0
is only generated for STIxy
is enabled and thus STIxy
0
0
1
is masked, the STOVxy0 is generated for any other
and is only generated if STIxy
1
are both generated due to STIxy
2)
1
is enabled with the result that STOVxy
in the STI register.
is only generated due to STIxy
0
37
and xy
0
1
is disabled in example 6, so STOVxy
is enabled, and therefore STOVxy
1
are used to refer to two different
0
1
is only generated. If no STI is
but not for STIxy
Functional Description
h
for monitoring from DU
0
PEF 82912/82913
1)
is enabled and not
0
and synchronous
1
.
.
0
.
2001-03-30
0
is only
0
0
1
0
is
is
is
is