PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 42

• Manufacturer Part Number: PEF82912FV14XP
• Manufacturer: Lantiq

Specifications of PEF82912FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

2.3
The Q-SMINT I supports the IOM -2 interface in terminal mode (DCL=1.536 MHz)
according to the IOM -2 Reference Guide [13].
2.3.1
The IOM -2 interface consists of four lines: FSC, DCL, DD, DU and optionally BCL. The
rising edge of FSC indicates the start of an IOM -2 frame. The DCL and the BCL clock
signals synchronize the data transfer on both data lines DU and DD. The DCL is twice
the bit rate, the BCL rate is equal to the bit rate. The bits are shifted out with the rising
edge of the first DCL clock cycle and sampled at the falling edge of the second clock
cycle. With BCL the bits are shifted out with the rising edge and sampled with the falling
edge of the single clock cycle.
The IOM -2 interface can be enabled/disabled with the DIS_IOM bit in the IOM_CR
register.
The FSC signal is an 8 kHz frame sync signal. The number of PCM timeslots on the
receive and transmit lines is determined by the frequency of the DCL clock (or BCL), with
the 1.536 MHz (BCL=768 kHz) clock 3 channels consisting of 4 timeslots each are
available.
IOM
The frame structure on the IOM -2 data ports (DU,DD) of the Q-SMINT I with a DCL
clock of 1.536 MHz (or BCL=768 kHz) and if TIC bus is not disabled (IOM_CR.TIC_DIS)
is shown in
•
Figure 10
Data Sheet
®
-2 Frame Structure of the Q-SMINT I
IOM -2 Interface
IOM -2 Functional Description
Figure
IOM -2 Frame Structure of the Q-SMINT I
10.
28
Functional Description
PEF 82912/82913
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2001-03-30